s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 15

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

Bits 0 to 2: Speed
Bit 3: Reserved
Bits 4 to 7: Delay
7.1.2.5 Register 4
Bit 0: Link Control
Bit 1: Contender
Bits 2 to 4: Jitter
Bits 5 to 7: Power Class
Rev. 1.0
The maximum transmission speed the SIR72900F00A supports. Normally, 2 ('010b') is read.
The SIR72900F00A's repeat delay in the worst cases. Normally, 2 ('0010b') is read.
The maximum repeat delay time of the SIR72900F00A is 0.184 s.
This bit controls the value of the L (link_active) field of the Self-ID packet. The L (link_active) field of the Self-ID
packet reflects the logical multiplication between this bit and LPS signal.
This bit is initialized to '1' as bus reset occurs.
This bit reflects the c (CONTENDER) field of the Self-ID packet. This bit has the same meaning as the c
(CONTENDER) field of the Self-ID packet.
This bit reflects the value of the BCLKON pin when hardware reset occurs.
A difference between the maximum and minimum repeat delays of the SIR72900F00A. Normally, 0'000b' is read.
The repeat jitter of the SIR72900F00A is 20 ns.
These bits reflect the pwr (POWER_CLASS) field of the Self-ID packet. They have the same meaning as the pwr
(POWER_CLASS) field of the Self-ID packet.
These bits are initialized to the value of pins PS0, PS1, and PS2 when hardware reset occurs.
The relationships between the bits and pins PS0, PS1, and PS2 are as follows:
Address
0x04
bit5:PS0(Pin22)
bit6:PS1(Pin21)
bit7:PS2(Pin20)
0: LCtrl
1: Contender
2: Jitter [0]
3: Jitter [1]
4: Jitter [2]
5: Power_class [0]
6: Power_class [1]
7: Power_class [2]
Bit Symbol
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Power Reset Value
EPSON
See discription
1
0
0
0
0
0
0
Contender
Link Control
Jitter
Jitter
Jitter
Power Class
Power Class
Power Class
Description
S1R72900F00A
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