S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet
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... S1D13700F02 Embedded Memory Graphics LCD Controller Hardware Functional Specification Document Number: X42D-A-001-01 Status: Revision 1.01 Issue Date: 2005/11/29 © SEIKO EPSON CORPORATION 2005. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13700F02 X42D-A-001-01 Epson Research and Development Revision 1.01 Vancouver Design Center Hardware Functional Specification Issue Date: 2005/11/29 ...
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... MC68K Family Bus Direct/Indirect Interface with DTACK# Timing . . . . . . . . 30 7.3.4 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing . . . . . . 32 7.3.5 M6800 Family Bus Indirect Interface Timing . . . . . . . . . . . . . . . . . . . . 34 7.4 Power Save Mode/Display Enable Timing . . . . . . . . . . . . . . . . . . . 36 7.5 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Hardware Functional Specification Issue Date: 2005/11/29 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision 1.01 Page 3 S1D13700F02 X42D-A-001-01 ...
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... Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12 Display Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 12.1 Character Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .76 12.2 Screen Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 12.2.1 Screen Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.2.2 Display Address Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.2.3 Display Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3 Cursor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 12.3.1 Cursor Write Register Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.3.2 Cursor Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 S1D13700F02 X42D-A-001-01 Epson Research and Development Revision 1.01 Vancouver Design Center Hardware Functional Specification Issue Date: 2005/11/29 ...
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... Half-Tone Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 15.4.3 Flash Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 15.5 16 ¥ 16-Dot Graphic Display 15.5.1 Command Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 15.5.2 Kanji Character Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 16 Internal Character Generator Font 17 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Hardware Functional Specification Issue Date: 2005/11/ 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 . . . . . . . . . . . . . . . . . . . . . . . . 115 . . . . . . . . . . . . . . . . . . . . . . . . 120 . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Revision 1.01 Page 5 S1D13700F02 X42D-A-001-01 ...
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... Page 6 18 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 20 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 20.1 Epson LCD Controllers (S1D13700F02) 20.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 S1D13700F02 X42D-A-001-01 Epson Research and Development . . . . . . . . . . . . . . . . . . . 128 Revision 1.01 Vancouver Design Center Hardware Functional Specification Issue Date: 2005/11/29 ...
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... We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com. 1.2 Overview Description The S1D13700F02 can display both text and graphics on an LCD panel. The S1D13700F02 allows layered text and graphics, scrolling of the display in any direction, and partitioning of the display into multiple screens. It includes 32K bytes of embedded SRAM display memory which is used to store text, character codes, and bit-mapped graphics ...
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... Three overlapping screens in graphics mode • Programmable cursor control • Smooth horizontal scrolling of all or part of the display in monochrome mode • Smooth vertical scrolling of all or part of the display in all modes S1D13700F02 X42D-A-001-01 Epson Research and Development Revision 1.01 Vancouver Design Center ...
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... 2.7 Clock Source • Two terminal crystal or Single Oscillator input Input Clock (maximum 60 MHz) FPSHIFT Clock (maximum 15 MHz) 2.8 Package • TQFP13 - 64-pin Pb-free package (lead free) Hardware Functional Specification Issue Date: 2005/11/29 3.0 to 3.6 volts DD 3.0 to 5.5 volts Revision 1.01 Page 9 S1D13700F02 X42D-A-001-01 ...
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... Page 10 3 System Diagrams Generic Bus (Indirect) CS# Axx A0 D[15:8] D[7:0] RD0# RD1# WR0# WR1# WAIT# RESET# Figure 3-1 Indirect Generic to S1D13700F02 Interface Example Generic Bus (Direct) CS# A[15:0] D[15:8] D[7:0] RD0# RD1# WR0# WR1# WAIT# RESET# Figure 3-2 Direct Generic to S1D13700F02 Interface Example S1D13700F02 X42D-A-001-01 S1D13700F02 CNF4 AS# ...
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... Epson Research and Development Vancouver Design Center MC68K (Indirect) AS# FC[2:0] A[23:1] A0 D[15:8] D[7:0] UDS# LDS# R/W# DTACK# RESET# Figure 3-3 Indirect MC68K to S1D13700F02 Interface Example MC68K (Direct) AS# FC[2:0] A[23:16] A[15:0] D[15:8] D[7:0] UDS# LDS# R/W# DTACK# RESET# Figure 3-4 Direct MC68K to S1D13700F02 Interface Example Hardware Functional Specification Issue Date: 2005/11/29 S1D13700F02 CNF4 AS# ...
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... Page 12 M6800 (Indirect) VMA# A[16:1] A0 D[15:8] D[7:0] E R/W# RESET# Figure 3-5 Indirect M6800 to S1D13700F02 Interface Example S1D13700F02 X42D-A-001-01 S1D13700F02 CNF4 AS# Decoder CS# A[15:1] A0 (command or parameter) D[7:0] RD# WR# WAIT# RESET# /RESET Revision 1.01 Epson Research and Development Vancouver Design Center CNF3 CNF2 Hardware Functional Specification Issue Date: 2005/11/29 ...
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... Address Generator Controller Hardware Functional Specification Issue Date: 2005/11/29 LCD Character Generator LCD Controller ROM Layered Layered GrayScale Controller FRM Controller Microprocessor Interface Host Microprocessor Figure 4-1 Functional Block Diagram Revision 1.01 Page 13 DotClock Generator Internal Clock Dot Counter Oscillator S1D13700F02 X42D-A-001-01 ...
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... VSS WAIT# HIOVDD CNF0 CNF1 CNF2 CNF3 CNF4 AS# A15 A14 A13 64 1 Figure 5-1 Pinout Diagram (TQFP13 - 64 pin) S1D13700F02 X42D-A-001-01 D1370002A1 Index Revision 1.01 Epson Research and Development Vancouver Design Center 33 NIOVDD 32 YDIS FPFRAME YSCL VSS MOD FPLINE COREVDD XECL FPSHIFT ...
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... Output buffer (6mA/-6mA@3.3V) with Test LIN TTL transparent input LOT TTL transparent output T1 Test mode control input with pull-down resistor (typical value of 50 kΩ@3.3V) HTB2T Tri-state output buffer (6mA/-6mA@3.3V) Hardware Functional Specification Issue Date: 2005/11/29 Table 5-1: Cell Descriptions Description Revision 1.01 Page 15 S1D13700F02 X42D-A-001-01 ...
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... S1D13700F02 when this clock goes high. • When the MC68K host bus interface is selected, this pin is the active-low lower data strobe (LDS#). Data is read from or written to the S1D13700F02 when this signal goes low. Revision 1.01 Epson Research and Development Vancouver Design Center ...
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... When the M6800 host bus interface is selected, this signal is the read/write control signal (R/W#). Data is read from HIOVDD — the S1D13700F02 if this signal is high, and written to the S1D13700F02 low. • When the MC68K host bus interface is selected, this signal is the read/write control signal (RD/WR#). Data is read from the S1D13700F02 if this signal is high, and written to the S1D13700F02 low ...
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... Page 18 5.2.2 LCD Interface In order to provide effective low-power drive for LCD matrixes, the S1D13700F02 can directly control both the X and Y-drivers using an enable chain. Pin Name Type Pin # Cell FPDAT[3:0] O 18-21 OB2T (XD[3:0]) FPSHIFT O 23 OB2T (XSCL) XECL O 24 OB2T FPLINE O 26 OB2T (LP) ...
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... State — — IO power supply for the Host (MPU) interface, 3.3/5.0 volts. — — IO power supply for the LCD interface, 3.3/5.0 volts. — — Core power supply, 3.3 volts. — — Ground for HIOVDD, NIOVDD, and COREVDD Revision 1.01 Page 19 Description Description S1D13700F02 X42D-A-001-01 ...
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... CNF3 CNF2 0 CNF[3: Select the FPSHIFT cycle time (FPSHIFT:Clock Input) as follows: CNF1 CNF0 0 CNF[1: S1D13700F02 X42D-A-001-01 Table 5-6: Summary of Configuration Options Configuration State DIrect Addressing Mode: Host Bus 0 Generic Bus 1 Reserved 0 M6800 Family Bus Interface 1 MC68K Family Bus Interface ...
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... HIOVDD HIOVDD Connected to Connected to Connected to VSS HIOVDD HIOVDD See Note See Note See Note Revision 1.01 Page 21 M6800 M6800 Direct Indirect Connected to VSS A0 D[7:0] External Decode Connected to HIOVDD E Not R/W# supported Unconnected RESET# Connected to HIOVDD Connected to HIOVDD Connected to VSS See Note S1D13700F02 X42D-A-001-01 ...
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... High Level Input Voltage IH1 V Low Level Input Voltage IL1 V High Level Input Voltage T+ V Low Level Input Voltage T- V Hysteresis Voltage H1 R Pull Down Resistance PD S1D13700F02 X42D-A-001-01 Table 6-1 Absolute Maximum Ratings Rating V - 0 0 ...
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... V -0.4 DD ⎯ ⎯ 0.4 ⎯ ⎯ 3.5 ⎯ ⎯ 1.0 ⎯ 2.0 4.0 ⎯ 0.8 3.1 ⎯ ⎯ 0 144 Cell Type OB2T CB2 HTB2T CI CID1 CB2 SI SI CID1 S1D13700F02 X42D-A-001-01 Page 23 Units μA μA μA μ kΩ ...
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... Input Clock Rise Time (10% - 90%) r Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI. For further details on internal clocks, see Sec- tion 9, “Clocks” on page 41. S1D13700F02 X42D-A-001-01 Core V = 3.3V ± 10 3.3V ± 10% or 5.0V ± 10% ...
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... Hardware Functional Specification Issue Date: 2005/11/ Normal Mode Table 7-2 Reset Timing Parameter S1D13700F02 cannot receive commands. Commands to initialize the Revision 1. Power Save Mode Min Max Units ⎯ ⎯ S1D13700F02 S1D13700F02 X42D-A-001-01 Page 25 ...
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... Page 26 7.3 CPU Interface Timing 7.3.1 Generic Bus Direct/Indirect Interface with WAIT# Timing CS# A[15:0] WR#, RD# WAIT# D[7:0] (write) D[7:0] (read) Figure 7-4 Generic Bus Direct/Indirect Interface with WAIT# Timing S1D13700F02 X42D-A-001- t13 t4 Valid t11 t5 Revision 1.01 Epson Research and Development Vancouver Design Center t6 t7 t12 t8 t9 ...
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... Note 2 Note 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ Note 5 Note 5 S1D13700F02 X42D-A-001-01 Page 27 Units ...
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... Page 28 7.3.2 Generic Bus Direct/Indirect Interface without WAIT# Timing CS# A[15:0] WR#, RD# D[7:0] (write) D[7:0] (read) Figure 7-5 Generic Bus Direct/Indirect Interface without WAIT# Timing S1D13700F02 X42D-A-001- t10 t11 t3 Valid t4 t9 Revision 1.01 Epson Research and Development Vancouver Design Center t5 t6 t12 t7 t8 Valid Hardware Functional Specification ...
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... Note 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ ⎯ ⎯ Note 5 Note 5 S1D13700F02 X42D-A-001-01 Page 29 Units ...
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... Page 30 7.3.3 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing CS# A[15:0], WR# (RW#, MR#) AS# RD# (UDS#, LDS#) WAIT# (DTACK#) D[7:0] (write) D[7:0] (read) Figure 7-6 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing S1D13700F02 X42D-A-001- t14 t3 t13 t4 t11 t5 Revision 1.01 Epson Research and Development Vancouver Design Center ...
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... Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ Note 5 Note 5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 6 0 Note 6 S1D13700F02 X42D-A-001-01 Page 31 Units ...
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... Page 32 7.3.4 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing CS# A[15:0], WR# (RW#, MR#) AS# RD# (UDS#, LDS#) D[7:0] (write) D[7:0] (read) Figure 7-7 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing S1D13700F02 X42D-A-001- t13 t10 t11 Revision 1.01 Epson Research and Development Vancouver Design Center ...
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... Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ ⎯ ⎯ Note 5 Note 5 ⎯ ⎯ ⎯ ⎯ S1D13700F02 X42D-A-001-01 Page 33 Units ...
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... Page 34 7.3.5 M6800 Family Bus Indirect Interface Timing CS# A[15:0], WR# (RW#) RD# (E) D[7:0] (write) D[7:0] (read) Figure 7-8 M6800 Family Bus Indirect Interface Timing S1D13700F02 X42D-A-001- t10 t11 Revision 1.01 Epson Research and Development Vancouver Design Center t5 t6 t12 t7 t8 Hardware Functional Specification Issue Date: 2005/11/29 ...
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... Note 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ ⎯ ⎯ Note 5 Note 5 S1D13700F02 X42D-A-001-01 Page 35 Units ...
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... YDIS rising edge delay for Display On (see Note System Clock Period 2. Power Save Mode is controlled by the Power Save Mode Enable bit, REG[08h] bit 0. 3. Display On/Off is controlled by the Display Enable bit, REG[09h] bit 0. S1D13700F02 X42D-A-001-01 t1 Display Off or Power Save Mode Enabled 3.0 Volt Min. ⎯ ...
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... FPDAT0 Invalid XECL Figure 7-10: Monochrome 4-Bit Panel Timing Hardware Functional Specification Issue Date: 2005/11/29 VDP (1 Frame) LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 1 Line HDP 1-1 1-5 1-2 1-6 1-3 1-7 1-4 1-8 Revision 1.01 Page 37 Invalid LINE1 LINE2 HNDP 1-317 Invalid 1-318 Invalid 1-319 Invalid 1-320 Invalid S1D13700F02 X42D-A-001-01 ...
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... Page 38 FPSHIFT (XSCL) FPDAT3 FPDAT2 FPDAT1 FPDAT0 FPLINE (LP) XECL MOD (WF(B)) FPFRAME (YD) YSCL S1D13700F02 X42D-A-001- t11 t12 t13 t15 t16 Revision 1.01 Epson Research and Development Vancouver Design Center t10 t14 Hardware Functional Specification Issue Date: 2005/11/29 ...
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... ⎯ 0.25Tc - 4 ns ⎯ 0.75Tc - 4 ns ⎯ Note 2 ns ⎯ 0.75Tc - 4 ns ⎯ ⎯ 2Tc - 10 ns ⎯ 2Tc ns ⎯ 3Tc - 10 ns ⎯ S1D13700F02 X42D-A-001-01 ...
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... Page 40 8 Memory Mapping The S1D13700F02 includes 32K bytes of embedded SRAM. The memory is used for the display data, the registers and the CGROM. 0000h 7FFFh 8000h 802Fh 8030h FFFFh S1D13700F02 X42D-A-001-01 (MSB) D7 DISPLAY RAM Area Register Area Not Used Figure 8-1 S1D13700F02 Memory Mapping Revision 1 ...
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... Epson Research and Development Vancouver Design Center 9 Clocks 9.1 Clock Diagram The following figure shows the clock tree of the S1D13700F02. CLKI Internal OSC Power Save Mode (REG[08h] bit 0) FPSHIFT Cycle Time (CNF[1:0] see Note) Note The FPSHIFT Cycle Time is configured using the CNF[1:0] pins. For further informa- tion, see Section 5.3, “ ...
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... Diagram,” on page 41. The maximum frequency possible for FPSHIFT clock is 15MHz. 9.3 Oscillator Circuit The S1D13700F02 design incorporates an oscillator circuit. A stable oscillator can be constructed by connecting an AT-cut crystal, two capacitors, and two resistors to XCG1 and XCD1, as shown in the figure below. If the oscillator frequency is increased, Cd and Cg should be decreased proportionally ...
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... Epson Research and Development Vancouver Design Center 10 Registers 10.1 Register Set The S1D13700F02 registers are listed in the following table. Register REG[00h] Memory Configuration Register REG[02h] Vertical Character Size Register REG[04h] Total Character Bytes Per Row Register REG[06h] Horizontal Address Range Register 0 REG[08h] Power Save Mode Register ...
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... Section 15.1.2, “Initialization Example” on page 104. SYSTEM SET The SYSTEM SET command is used to configure the S1D13700F02 for the display used and to exit power save mode when indirect addressing is used. The values from REG[00h] through REG[07h] are passed as parameters when the SYSTEM SET command is issued. For further information on the SYSTEM SET command, see Section 11.1.1, “ ...
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... This bit causes the S1D13700F02 to offset the text screen against the graphics back layer by one vertical pixel. To shift the text screen horizontally, the horizontal pixel scroll function (REG[1Bh] or the HDOT SCR command for indirect addressing) can be used to shift the text screen pixels to the right ...
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... This bit specifies the LCD panel drive method. When this bit = 0, a single panel drive is selected. When this bit = 1, a dual panel drive is selected. The following diagrams show examples of the possible drive methods. XECL FPFRAME Y driver S1D13700F02 X42D-A-001-01 XECL X driver FPFRAME Y driver LCD ...
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... Second screen block (Start Address = REG[0Eh], REG[0Fh]) Third screen block (Start Address = REG[11h], REG[12h]) Fourth screen block (Start Address = REG[13h], REG[14h]) Above-and-below configuration: continuous movement over Revision 1.01 Dual Panel (REG[00h] bit REG[00h] bit (IV) REG[03h] bits 7-0 REG[04h] bits 7-0 REG[05h] bits 7-0 whole screen S1D13700F02 X42D-A-001-01 Page 47 ...
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... These bits define the horizontal size, or width, of each character, in pixels. REG[01h] bits 3-0 = Horizontal Character Size in pixels - 1 The S1D13700F02 handles display data in 8-bit units, therefore characters larger than 8 pixels wide must be formed from 8-pixel segments. The following diagram shows an example of a character requiring two 8-pixel segments where the remainder of the second eight bits are not displayed ...
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... TC/R must be programmed such that the following formulas are valid. Hardware Functional Specification Issue Date: 2005/11/ Character Bytes Per Row bits 7 Total Character Bytes Per Row bits 7 [TC/R] ≥ [C/ ≤ TC/R ≤ 255 Revision 1.01 Page 49 Read/Write Vertical Character Size bits 3 Read/Write Read/Write S1D13700F02 X42D-A-001-01 ...
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... The following diagram demonstrates the relationship between the Horizontal Address Range and the Character Bytes Per Row value. Where: C/R = character bytes per row (REG[03h] bits 7- horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) Figure 10-5 Horizontal Address Range and Character Bytes Per Row Relationship S1D13700F02 X42D-A-001-01 Frame Height bits 7 ...
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... Epson Research and Development Vancouver Design Center POWER SAVE The POWER SAVE command is used to enter power save mode on the S1D13700F02 when indirect addressing is used. For further information on the POWER SAVE command, see Section 11.1.2, “POWER SAVE” on page 71. Note When indirect addressing is used, the SYSTEM SET command is used to exit power save mode. For further information on the SYSTEM SET command, see Section 11.1.1, “ ...
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... Default = 00h SAD3 Attribute bits 1 bits 7-6 SAD3 Attribute (FP 5-4) bits [1:0] These bits control the attributes of the third screen block (SAD3) as follows. REG[0Ah] bit S1D13700F02 X42D-A-001-01 n SAD2 Attribute bits 1-0 SAD1 Attribute bits 1 Table 10-3 Screen Block 3 Attribute Selection ...
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... Flash (approx. 1 Hz) Revision 1.01 Attributes OFF (Blank) No Flashing Flash (approx. 2 Hz) Flash (approx. 16 Hz) Attributes OFF (Blank) No Flashing Flash (approx. 2 Hz) Flash (approx. 16 Hz S1D13700F02 X42D-A-001-01 Page 53 ...
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... These bits determine the size of screen block 1, in lines. REG[0Dh] bits 7-0 = screen block 1 size in number of lines - 1 Note The relationship between the screen block start address (SADx), screen block size (SLx), and the display mode is described in Table 10-7 “Display Modes,” on page 57. S1D13700F02 X42D-A-001-01 Screen Block 1 Start Address bits 7-0 (LSB ...
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... Table 10-7 “Display Modes,” on page 57. Hardware Functional Specification Issue Date: 2005/11/29 Screen Block 2 Start Address bits 7-0 (LSB Screen Block 2 Start Address bits 15-8 (MSB Screen Block 2 Size bits 7 Revision 1.01 Page 55 Read/Write Read/Write Read/Write S1D13700F02 X42D-A-001-01 ...
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... These bits determine the memory start address of screen block 4. Note When the start address is changed, the LSB must be programmed before the MSB. The start address does not change until the MSB is written. S1D13700F02 X42D-A-001-01 Screen Block 3 Start Address bits 7-0 (LSB) 5 ...
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... Set both SL1 and SL2 to ([L/ Screen Configuration Example Graphics display page 2 Character or Graphics display page 1 Graphics display page 4 Character or Graphics display page 3 Layer 1 Layer 2 Revision 1.01 Second Layer SAD2 SL2 SAD2, SL2 SAD4 (see note 2) (SAD4) S1D13700F02 X42D-A-001-01 Page 57 ...
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... The parameters corresponding to SL3 and SL4 are fixed by REG[05h] bits 7-0 (L/F) and do not have to be set dual panel is selected (REG[00h] bit 3 = 1), the differences between SL1 and (L ÷ 2, and between SL2 and (L ÷ 2, are blanked. S1D13700F02 X42D-A-001-01 Table 10-7 Display Modes (Continued) First Layer SAD1, SL1 — ...
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... SL1 = screen block 1 size (REG[0Dh] bits 7-0) L/F = (REG[05h] bits 7-0) CSRFORM The CSRFORM command is used to configure the S1D13700F02 cursor when indirect addressing is used. The values from REG[15h] through REG[16h] are passed as parameters when the CSRFORM command is issued. For further information on the CSRFORM command, see Section 11.1.5, “CSRFORM” on page 72. ...
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... For a block cursor (REG[16h] bit 7 = 1), these bits set the height (or vertical size) of the cursor, in lines from the character origin (see Figure 10-7 “Cursor Size and Position,” on page 59). REG[16h] bits 3-0 = cursor height in lines - 1 Note The vertical cursor size must be less than or equal to the vertical character size. (REG[16h] bits 3-0 <= REG[02h] bits 3-0) S1D13700F02 X42D-A-001- n/a 5 ...
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... AP = Horizontal Address Range (REG[06h] bits 7-0, REG[07h] bits 7-0) Figure 10-8 Cursor Direction Table 10-8 Cursor Shift Direction Indirect Mode Shift Direction Command Bit Revision 1.01 Read/Write Cursor Shift Direction bits 1 Right Left Up Down S1D13700F02 X42D-A-001-01 Page 61 0 ...
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... This bit determines the display mode for screen block 1. When this bit = 0, screen block 1 is configured for text mode. When this bit = 1, screen block 1 is configured for graphics mode. Note Screen blocks 2 and 4 can display graphics only. S1D13700F02 X42D-A-001-01 3 Layer Overlay Screen Block 3 Select ...
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... Underlining, rules, mixed text and graphics ⊕ ∪ L2) L3 Exclusive-OR Inverted characters, flashing regions, underlining ∩ ∪ L2) L3 AND Simple animation, three-dimensional appearance ⎯ ⎯ Layer 2 Layer 3 Revision 1.01 Applications Reserved Visible display EPSON OR EPSON Exclusive OR SON AND S1D13700F02 X42D-A-001-01 Page 63 ...
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... For example, to determine the address of a 8x8 character at character code index 80h with a CGRAM start address of 6000h, the following calculation can be used. character start = (character code index x character height) + CGRAM start address The character starts in RAM at address 6400h and takes 8 memory locations. S1D13700F02 X42D-A-001-01 CGRAM Start Address bits 7-0 (LSB) 5 ...
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... Hardware Functional Specification Issue Date: 2005/11/29 n Display width M/N is the number of bits (dots) that parameter 1 (P1) is incremented/decremented by. Figure 10-10 Horizontal Scrolling Revision 1.01 Read/Write Horizontal Pixel Scroll bits 2 S1D13700F02 X42D-A-001-01 Page 65 0 ...
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... The cursor address register can only be modified by the CSRW command, and by the automatic increment after an MREAD or MWRITE command not affected by display scrolling new address is not set, display memory accesses are from the last set address or the address after previous automatic increments. S1D13700F02 X42D-A-001-01 Cursor Write bits 7-0 (LSB ...
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... Once for the low byte and then again for the high byte of the register. Hardware Functional Specification Issue Date: 2005/11/29 Cursor Read bits 7-0 (LSB Cursor Read bits 15-8 (MSB Revision 1.01 Page 67 Read Only Read Only S1D13700F02 X42D-A-001-01 ...
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... These bits select the bit-per-pixel mode as follows. If the CGRAM is used (includes CGRAM1 and CGRAM2), only 1 bpp is supported. Note The horizontal character size (REG[01h] bits 3-0) must be set to 7h and the Horizontal Pixel Scroll bits (REG[1Bh] bits 2-0) must be set to 0. S1D13700F02 X42D-A-001-01 n ...
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... Command write 1 0 Display data and cursor address read 0 0 Display data and parameter write Revision 1.01 Page 69 Control Byte No. of Bytes Value 40h 8 53h 0 58h 1 59h 44h 10 5Dh 2 4Ch - 4Fh 0 5Bh 1 5Ch 46h 2 47h 2 60h 1 42h n/a 43h S1D13700F02 X42D-A-001-01 ...
Page 70
... See Section , “SYSTEM SET” on page 44 for further information. Note If the S1D13700F02 is in power save mode (at power up or after a POWER SAVE com- mand), the SYSTEM SET command will exit power save mode. After writing the SYS- TEM SET command and its 8 parameters, the S1D13700F02 will be in normal operation ...
Page 71
... REG[0Ah] bits 7-0 bit 5 bit 4 bit 3 bit 2 bit REG[0Ah] bits 7-0 Revision 1.01 LSB bit 0 Indirect 1 C LSB bit 0 Indirect LSB bit 0 Indirect S1D13700F02 X42D-A-001-01 Page 71 ...
Page 72
... CSRFORM See “CSRFORM” on page 59 for further information. Table 11-10 CSRFORM Command and Parameters MSB bit 7 bit Note the Cursor Mode bit, REG[16h] bit 7. S1D13700F02 X42D-A-001-01 LSB bit 4 bit 3 bit 2 bit 1 bit ...
Page 73
... OV DM2 DM1 MX1 LSB bit 4 bit 3 bit 2 bit 1 bit A12 A11 A10 A9 A8 Revision 1.01 Page 73 LSB bit 0 Indirect CD0 C LSB bit 0 Indirect MX0 P1 Indirect C (SAGL) P1 (SAGH) P2 S1D13700F02 X42D-A-001-01 ...
Page 74
... Table 11-15 CSRW Command and Parameters MSB bit 7 bit A15 A14 11.1.11 CSRR See “CSRR” on page 67 for further information. MSB bit 7 bit 6 bit A15 A14 S1D13700F02 X42D-A-001-01 bit 5 bit 4 bit 3 bit 2 bit LSB bit 5 bit 4 ...
Page 75
... Memory Control See “Drawing Control Registers” on page 66 for further information. Hardware Functional Specification Issue Date: 2005/11/29 bit 5 bit 4 bit 3 bit 2 bit BPP1 BPP0 Revision 1.01 LSB bit 0 Indirect S1D13700F02 X42D-A-001-01 Page 75 ...
Page 76
... If the area outside the character bitmap contains only zeros, the displayed character size can be increased by increasing the horizontal character size (REG[01h] bits 3-0) and the vertical character size (REG[01h] bits 3-0). The zeros ensure that the extra space between displayed characters is blank. S1D13700F02 X42D-A-001- ...
Page 77
... Figure 12-2 Character Width Greater than One Byte Wide ([FX Note The S1D13700F02 does not automatically insert spaces between characters. If the dis- played character size is 8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row, even though the character image requires only one ...
Page 78
... Page 78 12.2 Screen Configuration 12.2.1 Screen Configuration The S1D13700F02 can be configured for a single text screen, overlapping text screens, or overlapping graphics screens. Graphics screens use eight times as much display memory as a text screen in 1 bpp. Figure 12-3 shows the relationship between the virtual screens and the physical screen ...
Page 79
... Vancouver Design Center 12.2.2 Display Address Scanning The S1D13700F02 scans the display memory in the same way as a raster scan CRT screen. Each row is scanned from left to right until the address range equals C/R, REG[03h] bits 7- 0. Rows are scanned from top to bottom. When in graphics mode, at the start of each line the address counter is set to the address at the start of the previous line plus the horizontal address range (or address pitch), REG[06h] - REG[07h] ...
Page 80
... Figure 12-5 Display Addressing in Graphics Mode Example Note In 1 bpp, one bit of display memory corresponds to one pixel. Therefore, 1 byte of dis- play memory corresponds to 8 pixels bpp, 1 byte corresponds to 4 pixels bpp, 1 byte corresponds to 2 pixels. S1D13700F02 X42D-A-001-01 SAD + 2 SAD + C/R SAD + AP ...
Page 81
... Assumes REG[00h] bit REG[01h] bits 3 REG[02h] bits 3 Figure 12-6 Dual Panel Display Address Indexing in Text Mode Note In dual panel drive, the S1D13700F02 reads line 1a and line 1b as one cycle. The upper and lower panels are thus read alternately, one line at a time. Hardware Functional Specification ...
Page 82
... Page 82 12.2.3 Display Scan Timing During display scanning, the S1D13700F02 pauses at the end of each line for TC/R - C/R ((REG[04h] bits 7-0) - (REG[03h] bits 7-0)) display memory read cycles, although the LCD drive signals are still generated. TC/R may be set to any value within the constraints imposed by C/R, Input Clock (CLK used to fine tune the frame frequency ...
Page 83
... Cursor Display Layers Although the S1D13700F02 can display up to three layers, the cursor is displayed in only one of these layers. For a two layer configuration (REG[18h] bit 4 = 0), the cursor is displayed in the first layer (L1). For a three layer configuration (REG[18h] bit 4 = 1), the cursor is displayed in the third layer (L3) ...
Page 84
... Page 84 Although the cursor is normally displayed for character data, the S1D13700F02 may also display a dummy cursor for graphical characters. This is only possible if a graphics screen is displayed, the text screen is turned off, and the microprocessor generates the cursor control address. D (REG[09h] bit ...
Page 85
... Memory to Display Relationship The S1D13700F02 supports virtual screens that are larger than the physical size of the LCD panel address range (C/R), REG[03h] bits 7-0. A layer of the S1D13700F02 can be considered as a window into the larger virtual screen held in display memory. This window can be divided into two blocks, with each block able to display a different portion of the virtual screen ...
Page 86
... Display page 1 Layer 1 Layer 2 Layer 3 Where: SADx = start address of screen block horizontal address range (REG[06h], REG[07h]) C/R = number of character bytes per row (REG[03h]) Figure 12-11 Screen Layers and Memory Relationship S1D13700F02 X42D-A-001-01 AP C/R SAD1 Character page 1 SAD3 Character page 3 SAD2 Graphics page 2 ...
Page 87
... L/F = frame height is 256 (REG[05h] bits 7- horizontal address range (or address pitch) is 64K bytes (REG[06h] bits 7-0, REG[07h] bits 7-0) Figure 12-12 Virtual Display (Display Window to Memory Relationship) Hardware Functional Specification Issue Date: 2005/11/29 AP CRY Display window C/R Revision 1.01 Page 87 Virtual display memory limit FFFFh S1D13700F02 X42D-A-001-01 ...
Page 88
... SAD2 Page 1 SL2 2000 2800 Back layer Page 2 4440 SAG 4800 CG RAM 4A00 Not used 802F Internal ROM 8030 Figure 12-13 Memory Map and Magnified Characters S1D13700F02 X42D-A-001- (Code) 0000 02FF 0080 (MSB) D7 1FFF D7 D0 01110000 ...
Page 89
... On-Page Scrolling The normal method of scrolling within a page is to move the whole display up one line and erase the bottom line. However, the S1D13700F02 does not automatically erase the bottom line must be erased with blanking data when changing the scroll address register. ...
Page 90
... Before scrolling WXYZ WXYZ After scrolling Where: SADx = start address of screen block horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) S1D13700F02 X42D-A-001-01 SAD1 789 789 SAD1 Figure 12-15 Inter-Page Scrolling Revision 1.01 Epson Research and Development ...
Page 91
... AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Figure 12-16 Horizontal Wraparound Scrolling Hardware Functional Specification Issue Date: 2005/11/29 Display XYZ SAD1 XYZ1 SAD1 Revision 1.01 Page 91 Display memory ABC XYZ 123 AP C/R ABC XYZ 123 S1D13700F02 X42D-A-001-01 ...
Page 92
... BC Before scrolling EFG TUV FG After scrolling TUV Where horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) S1D13700F02 X42D-A-001- 1234 56 Figure 12-17 Bi-Directional Scrolling Revision 1.01 Epson Research and Development Vancouver Design Center Display memory ...
Page 93
... The following table summarizes the units, or steps, that can be scrolled for each mode. Mode Text Graphics Note In a divided screen, each block cannot be independently scrolled horizontally in pixel units. Hardware Functional Specification Issue Date: 2005/11/29 Table 12-1 Scrolling Unit Summary Vertical Characters Pixels Revision 1.01 Page 93 Horizontal Pixels or Characters Pixels S1D13700F02 X42D-A-001-01 ...
Page 94
... Case 2 Line Line 2 Where: [CR [TCR [AP HDOTSCR = Disable FPSHIFT = 4 CLK Figure 12-18 Horizontal Pixel Scrolling Use Cases S1D13700F02 X42D-A-001-01 Case 3 Line 1 Line 2 Where: [CR [TCR [AP HDOTSCR = Enable FPSHIFT = 3 CLK Case 4 Line 1 D Line 2 H Where: ...
Page 95
... CG Characteristics 13.1.1 Internal Character Generator The internal character generator is recommended for minimum system configurations containing a S1D13700F02, display RAM, LCD panel, single-chip microprocessor and power supply. Since the internal character generator uses a CMOS mask ROM also recommended for low-power applications. • pixel font (See Section 16, “Internal Character Generator Font” on page 124) • ...
Page 96
... Table 13-2 Character Fonts Where Number of Lines ≤ 16 (REG[00h] bit SAG A15 A14 A13 A12 A11 A10 Character Code 0 0 +ROW Select Address 0 0 CGRAM Address VA15 VA14 VA13 VA12 VA11 VA10 VA9 S1D13700F02 X42D-A-001- ...
Page 97
... Lines = 1: lines in the character bitmap Lines = 2: lines in the character bitmap Hardware Functional Specification Issue Date: 2005/11/ Line Figure 13-1 Row Select Address ≤ 8. ≥ 9. Revision 1.01 Page 97 Line 2 S1D13700F02 X42D-A-001-01 ...
Page 98
... CGRAM. As characters cannot be used if only using graphics mode, there is no need to set the CGRAM data. CGRAM ADR CSRDIR CSRW MWRITE P16 S1D13700F02 X42D-A-001-01 start address is 4800h. The character code for the defined pattern is 80h (the first character code in the CGRAM area). Table 13-3 Character Data Example 5Ch P1 ...
Page 99
... < L ¥ → > ← CGRAM1 Figure 13-2 On-Chip Character Codes Revision 1. CGRAM2 S1D13700F02 X42D-A-001-01 Page 99 ...
Page 100
... The following table shows the signal states for each function 14.1.3 MC68K Family The following table shows the signal states for each function. A0 RD/WR# LDS S1D13700F02 X42D-A-001-01 Table 14-1 Generic Interface Signals RD# WR# Function 0 1 Display data and cursor address read 1 0 Display data and parameter write ...
Page 101
... B = RNDDN([C/R] x [FX] ÷ RNDUP(B ÷ 16 ÷ [FX ÷ Hardware Functional Specification Issue Date: 2005/11/29 and f FR Revision 1.01 Page 101 , and lines per frame [L/F] will also FR is given by one of the fol- SYSCLK S1D13700F02 X42D-A-001-01 ...
Page 102
... For 4 Bpp [ClockDiv] x Ffr x [L/ (Hz) SYSCLK where A = [TC/R] - [C/ RNDDN([C/R] x [FX] ÷ 16 RNDUP(B ÷ 16) For all cases above where: S1D13700F02 X42D-A-001-01 ClockDiv Ffr Frame Rate Revision 1.01 Epson Research and Development Vancouver Design Center ...
Page 103
... Note 1 The remaining pixels on the right-hand side of the display are automatically blanked by the S1D13700F02. There is no need to zero the display memory corresponding to these pixels. 2 Assumes a frame frequency of 70 Hz, 1 bpp, and a clock divide of 4. Hardware Functional Specification ...
Page 104
... Page 104 15.1.2 Initialization Example The initialization example shown below is for a S1D13700F02 with an 8-bit micropro- cessor interface bus and an Epson EG4810S-AR display unit (512 × 128 pixels). Indirect Addressing Note Set the cursor address to the start of each screen’s layer memory, and use MWRITE to fill the memory with space characters, 20h (text screen only) or 00h (graphics screen only). Determining which memory to clear is explained in Section 15.1.3, “ ...
Page 105
... Set horizontal pixel shift to zero (REG[1Bh] bits 2- Inverse video superposition (REG[18h] bits 1- First screen block is text mode (REG[18h] bit Third screen block is text mode (REG[18h] bit 3) Revision 1.01 Page 105 S1D13700F02 X42D-A-001-01 ...
Page 106
... C = 4Ch 14 MWRITE C = 42h P1 = 20h P2 = 45h P3 = 50h P4 = 53h S1D13700F02 X42D-A-001-01 Operation D: Display OFF (REG[09h] bit 0) FC1, FC0: Flash cursor (REG[0Ah] bits 1-0) First screen block ON (REG[0Ah] bits 3-2) Second and fourth screen blocks ON (REG[0Ah] bits 5-4) Third screen block ON (REG[0Ah] bits 7-6) Fill second screen layer memory with 00h (blank data) ...
Page 107
... Fill in a square to the left of the ‘E’ EPSON Set cursor address to 1001h (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) Fill in the second screen block in the second column of line 1 Repeat operations 18 and 19 to fill in the background under ‘EPSON’ (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) Revision 1.01 Page 107 S1D13700F02 X42D-A-001-01 ...
Page 108
... P7 = 74h P8 = 72h P9 = 69h P10 = 78h P11 = 20h P12 = 4Ch P13 = 43h P14 = 44h S1D13700F02 X42D-A-001-01 Operation Inverse display EPSON Set cursor to line three of the first screen block (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) Set cursor shift direction to right (REG[17h] bits 1-0) ‘D’ ...
Page 109
... Second layer (graphics): 320 ÷ characters per line, 200 ÷ 200 lines. Required memory size = 40 × 200 = 8000 bytes. Hardware Functional Specification Issue Date: 2005/11/29 03E8h 2nd graphics layer (8000 bytes) 0000h 1st character layer (1000 bytes) 03E7h Figure 15-2 Character Over Graphics Layers Revision 1.01 Page 109 2327h S1D13700F02 X42D-A-001-01 ...
Page 110
... OVLAY C = 5Bh P1 = 00h DISP ON/OFF C = 59h P1 = 16h X = Don’t care S1D13700F02 X42D-A-001-01 Epson Research and Development TC/R calculation fOSC = 6 MHz (refer to Section 15.1.1, “SYSTEM SET Command and Parameters” on page 101) fFR = 70 Hz (refer to Section 15.1.1, “SYSTEM SET Command and Parameters” on page 101) [TC/R] = 52, so TC/R = 34h Revision 1 ...
Page 111
... Second layer (graphics): 320 ÷ characters per line, 200 ÷ 200 lines. Required memory size = 8000 bytes. Hardware Functional Specification Issue Date: 2005/11/29 1F40h 2nd graphics layer (8000 bytes) 0000h 1st graphics layer (8000 bytes) 1F3Fh Figure 15-3 Two-Layer Graphics Revision 1.01 Page 111 3E7Fh S1D13700F02 X42D-A-001-01 ...
Page 112
... P2 = 87h HDOT SCR C = 5Ah P1 = 00h OVLAY C = 5Bh P1 = 0Ch DISP ON/OFF C = 59h P1 = 16h X = Don’t care S1D13700F02 X42D-A-001-01 Epson Research and Development TC/R calculation MHz (refer to Section 15.1.1, “SYSTEM SET OSC Command and Parameters” on page 101 (refer to Section 15.1.1, “SYSTEM SET FR Command and Parameters” ...
Page 113
... Hardware Functional Specification Issue Date: 2005/11/29 3E80h 3rd graphics layer (8000 bytes) 1F40h 2nd graphics layer (8000 bytes) 3E7Fh 1F3Fh Figure 15-4 Three-Layer Graphics Revision 1.01 Page 113 5DBFh S1D13700F02 X42D-A-001-01 ...
Page 114
... P2 = 87h HDOT SCR C = 5Ah P1 = 00h OVLAY C = 5Bh P1 = 1Ch DISP ON/OFF C = 59h P1 = 16h X = Don’t care S1D13700F02 X42D-A-001-01 Epson Research and Development TC/R calculation MHz (refer to Section 15.1.1, “SYSTEM SET OSC Command and Parameters” on page 101 (refer to Section 15.1.1, “SYSTEM SET FR Command and Parameters” ...
Page 115
... Smooth Horizontal Scrolling The S1D13700F02 supports smooth horizontal scrolling to the left as shown in Figure 15-5 “HDOT SCR Example,” on page 116. When scrolling left, the screen is effectively moving to the right over the larger virtual screen. ...
Page 116
... AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Note The response time of LCD panels changes considerably at low temperatures. Smooth scrolling under these conditions may make the display difficult to read. S1D13700F02 X42D-A-001-01 SAD SAD + 1 SAD + 2 Magnified ...
Page 117
... Epson Research and Development Vancouver Design Center 15.4 Layered Display Attributes S1D13700F02 incorporates a number of functions for enhancing displays using monochrome LCD panels. It allows the display of inverse characters, half-intensity menu pads and flashing of selected screen areas. These functions are controlled by REG[18h] Overlay Register and REG[0Ah] Display Attribute Register. ...
Page 118
... The difference in contrast between the half and full intensity displays make it easy to distinguish between the two graphs and create an attractive display. 1. REG[18h] Overlay Register = 00h 2. REG[0Ah] Display Attribute Register = 34h S1D13700F02 X42D-A-001-01 SAD2 + 2nd layer Revision 1 ...
Page 119
... Flash the layer 2 screen block for the area to be flashed and combine the layers using the OR function. ABC Hardware Functional Specification Issue Date: 2005/11/29 XYZ Figure 15-8 Flash Attribute for a Large Area Revision 1.01 ABC XYZ S1D13700F02 X42D-A-001-01 Page 119 ...
Page 120
... To write large characters, use the following procedure. For further information, see the flowchart in Figure 15-9 “Graphics Address Indexing,” on page 121. 1. Reads the character data from the CGRAM 2. Set the display address 3. Writes to the display memory S1D13700F02 X42D-A-001-01 Epson Research and Development Revision 1.01 Vancouver Design Center ...
Page 121
... Data written into the S1D13700F02 display memory Figure 15-9 Graphics Address Indexing Revision 1.01 Page 121 CGROM output (n) shows the CG data readout order (Kanji pattern) (4) (2) (3) (1) S1D13700F02 X42D-A-001-01 ...
Page 122
... The CGRAM data format is described in Figure 13 “Character Generator,” on page 95. This allows the display 128, 16 × 16 pixel characters. If CGRAM is also used, 96 fixed characters and 32 bank- switchable characters are also be supported. S1D13700F02 X42D-A-001-01 (2) (4) ...
Page 123
... Set column 1 cursor address Write data Set column 2 cursor address Write data End Start Enable cursor downwards movement Set column 1 cursor address Write data Set column 2 cursor address Write data End Figure 15-11 16 × 16-Dot Display Flowchart Revision 1.01 Page 123 S1D13700F02 X42D-A-001-01 ...
Page 124
... Note The shaded positions indicate characters that have the whole 6 × 8 bitmap blackened. S1D13700F02 X42D-A-001-01 Character code bits Figure 16-1 On-Chip Character Set Revision 1.01 Epson Research and Development Vancouver Design Center ...
Page 125
... The S1D13700F02 is removed from power save mode by writing a 0 the Power Save Mode Enable bit, REG[08h] bit 0. However, after disabling power save mode, one dummy write to any register must be performed for direct addressing mode, and at least two dummy writes must be performed for indirect addressing mode ...
Page 126
... Page 126 18 Mechanical Data Symbol E D Amax θ Figure 18-1 Mechanical Drawing TQFP13 - 64 pin S1D13700F02 X42D-A-001- INDEX Dimension in Millimeters Min Nom - 10 0.1 - 1.0 - 0.5 0.17 - 0.09 - 0° 1.0 - 12 Revision 1.01 Epson Research and Development Vancouver Design Center 33 32 ...
Page 127
... Epson Research and Development Vancouver Design Center 19 References The following documents contain additional information related to the S1D13700F02. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. • S1D13700 Product Brief (X42A-C-001-xx) ...
Page 128
... Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk// 20.2 Ordering Information To order the S1D13700F02 LCD Controller, contact the Epson sales representative in your area. S1D13700F02 X42D-A-001-01 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA ...
Page 129
... Revision 0.02 - Issued: November 18, 2005 • all changes from the last revision of the spec are highlighted in Red • fixed product number in footer, should be S1D13700F02 instead of S1D13700F01 • section 5.2, for all pin tables, changed the “RESET# State” column to “RESET#/Power On State” ...
Page 130
... For further information, refer to Section 7.2, “Reset Timing” on page 25.” • section 12.2.3 “Display Scan Timing”, removed note about possible flicker problems in text mode, this issue was fixed for the S1D13700F02 • S1D13700F02 ...