S1D13700F02 Epson Electronics America, Inc., S1D13700F02 Datasheet - Page 52

• Manufacturer Part Number: S1D13700F02
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 52
10.3.2 Display Control Registers
DISP ON/OFF
bit 0
bits 7-6
S1D13700F02
X42D-A-001-01
REG[09h] Display Enable Register
Address = 8009h
REG[0Ah] Display Attribute Register
Address = 800Ah
SAD3 Attribute bits 1-0
7
7
REG[0Ah] bit 7
6
6
Default = 00h
Default = 00h
0
0
1
1
These registers enable/disable the display, and control the cursor and layered screens.
The DISP ON/OFF command is used to enable/disable the display and display attributes
when indirect addressing is used. The values from REG[0Ah] are passed as parameters
when the DISP ON/OFF command is issued. For further information on the DISP ON/OFF
command, see Section 11.1.3, “DISP ON/OFF” on page 71.
Display Enable
This bit controls the LCD display, including the cursor and all layered screens. The dis-
play enable bit takes precedence over the individual attribute bits in the Display Attribute
register, REG[0Ah]. For information on LCD pin states when the display is off (REG[09h]
bit 0 = 0), see Table 17-1 “State of LCD Pins During Power Save Mode,” on page 125.
When this bit = 0, the display is off.
When this bit = 1, the display is on.
SAD3 Attribute (FP 5-4) bits [1:0]
These bits control the attributes of the third screen block (SAD3) as follows.
Table 10-3 Screen Block 3 Attribute Selection
SAD2 Attribute bits 1-0
5
5
REG[0Ah] bit 6
Third Screen Block (SAD3)
0
1
0
1
n/a
4
4
Revision 1.01
SAD1 Attribute bits 1-0
3
3
ON
OFF (Blank)
Attributes
2
2
Flash at f
Flash at f
(approx. 16 Hz)
(approx. 2 Hz)
No Flashing
Epson Research and Development
Hardware Functional Specification
FR
FR
/32 Hz
Cursor Attribute bits 1-0
/4 Hz
1
1
Vancouver Design Center
Issue Date: 2005/11/29
Read/Write
Read/Write
Display Enable
0
0