peb2025 ETC-unknow, peb2025 Datasheet - Page 10

• Manufacturer Part Number: peb2025
• Description: Isdn Exchange Power Controller
• Manufacturer: ETC-unknow

Figure 5
Open Loop Detection
Digital Part
The microprocessor interface (MPI) communicates with a processor which controles the IEPC. This
MPI contains a 3-bit data bus, a 2-bit address bus, read-, write-, chip select- and reset lines.
If chip select is inactive (logic high) the data bus is in a high impedance state and no communication
between the processor and IEPC is possible.
The IEPC contains a line oriented register architecture, i.e. one read and one write register for each
line. A read or write cycle affects the addressed register, which is related to the corresponding line
driver.
The write register consists of three control bits per line i:
D0: Automatic Restart-bit (AR)
D1: ON/OFF-bit (ON)
D2: must be 0
The read register consists of three status bits per line i:
D0: Interrupt-bit (INT)
D1: Actual ON/OFF Driver status-bit (AO)
D3: Current Overload-bit (CO)
A logic high on the RES pin sets the device into an inital state: all registers of the IEPC are cleared
(D0i - D2i are low).
Semiconductor Group
10
PEB 2025