psb21391 Infineon Technologies Corporation, psb21391 Datasheet - Page 170

• Manufacturer Part Number: psb21391
• Description: Siemens Codec With Upn Transceiver
• Manufacturer: Infineon Technologies Corporation

Data Sheet
6.1
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO/SDS2. The selection of these reset sources can be done with
the RSS2,1 bits in the MODE1 register according table 23.
If RSS2,1 = ’01’ the RSTO/SDS2 pin has SDS2 functionality and a serial data strobe
signal (see chapter 2.2.3) is output at the RSTO/SDS2 pin. In this case only a hardware
reset or a reset generated by the undervoltage detection is output at RSTO/SDS2. The
internal reset sources set the MODE1 register to its default value.
Table 23
Reset Source Selection
• C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/
• EAW (Subscriber Awake)
• Watchdog Timer
RSS2
Bit 1
I0) generates a reset pulse of 125µs
A low pulse of at least 65 ns pulse width on the EAW input starts the oscillator from
the power down state and generates a reset pulse of 125 µs
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog
timer:
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset
pulse of 125 µs is generated.
If the watchdog timer is enabled (RSS = ’11’) the RSS bits can only be changed by a
hardware reset.
0
0
1
1
RSS1
Reset Source Selection
Bit 0
0
1
0
1
1.
2.
C/I Code
Change
WTC1
1
0
--
--
--
x
EAW
t
WTC2
0
1
160
--
--
--
x
250µs.
Watchdog
Timer
--
--
--
x
t
250 µs.
Functionality
PSB 21391
PSB 21393
SDS2
2001-03-07
--
--
--
x
Reset