psb21391 Infineon Technologies Corporation, psb21391 Datasheet - Page 214
psb21391
Manufacturer Part Number
psb21391
Description
Siemens Codec With Upn Transceiver
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PSB21391.pdf
(253 pages)
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Data Sheet
7.2.11
Value after reset: 00
STI
For all interrupts in the STI register following logical states are applied:
0: Interrupt is not activated
1: Interrupt is aestivated
STOVxy
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has
not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one
(for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for
the STOV.
STIxy
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous
Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock
after the selected time slot (TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
receive/transmit operations. One BCL clock is equivalent to two DCL clocks.
STI - Synchronous Transfer Interrupt
7
STOV
21
... Synchronous Transfer Overflow Interrupt
... Synchronous Transfer Interrupt
STOV
H
20
STOV
11
STOV
10
204
STI
21
STI
20
Detalled Register Description
STI
11
0
STI
10
PSB 21391
PSB 21393
2001-03-07
RD (58
H
)
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