at89c51snd1 ATMEL Corporation, at89c51snd1 Datasheet - Page 3

• Manufacturer Part Number: at89c51snd1
• Description: Mp3 Microcontrollers
• Manufacturer: ATMEL Corporation

ISP Communication
Management
User Call Management
Flash Memory Management
Bootloader
Configuration
Configuration and
Manufacturer Information
Mapping and Default Value of
Hardware Security Byte
4241B–MP3–07/04
The purpose of this process is to manage the communication and its protocol between
the on-chip bootloader and an external device (host). The on-chip bootloader imple-
ments a serial protocol (see Section “Protocol”, page 9). This process translates serial
communication frames (UART) into Flash memory accesses (read, write, erase, etc.).
Several Application Program Interface (API) calls are available to the application pro-
gram to selectively erase and program Flash pages. All calls are made through a
common interface (API calls) included in the bootloader. The purpose of this process is
to translate the application request into internal Flash memory operations.
This process manages low level accesses to the Flash memory (performs read and
write accesses).
The table below lists configuration and manufacturer byte information used by the boot-
loader. This information can be accessed through a set of API or ISP commands.
Table 1. Configuration and Munfacturer Byte Information
The 4 Most Significant Bytes (MSB) of the Hardware Byte can be read/written by soft-
ware (this area is called Fuse bits). The 4 Least Significant Bytes (LSB) can only be
read by software and written by hardware in parallel mode (with parallel programmer
devices).
Table 2. Mapping and Default Value of HSB
Note:
Mnemonic
BSB
SBV
SSB
Manufacturer
ID1: Family code
ID2: Product Name
ID3: Product Revision
Bit Position
7
6
5
4
3
2
1
0
U: Unprogrammed = 1, P: Program = 0
Mnemonic
Reserved
Reserved
Reserved
BLJB
X2B
LB2
LB1
LB0
Description
Boot Status Byte
Software Boot Vector
Software Security Byte
AT89C51SND1 UART Bootloader
Default Value
U
P
U
U
U
P
U
U
Description
To start in x1 mode
To map the boot area in code area between F000h-
FFFFh
To lock the chip (see datasheet)
Default Value
FCh
D7h
ECh
FFh
F0h
FFh
58h
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