cyv15g0403tb Cypress Semiconductor Corporation., cyv15g0403tb Datasheet - Page 8

• Manufacturer Part Number: cyv15g0403tb
• Description: Independent Clock Quad Hotlink Ii Serializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02104 Rev. *B
Pin Definitions
CYV15G0403TB Quad HOTLink II Serializer
WREN
ADDR[3:0]
DATA[4:0]
TXCKSEL[A..D] Internal Latch
TXRATE[A..D]
TXBIST[A..D]
OE2[A..D]
OE1[A..D]
PABRST[A..D]
GLEN[11..0]
FGLEN[2..0]
Factory Test Modes
SCANEN2
TMEN3
OUTA1±
OUTB1±
OUTC1±
OUTD1±
OUTA2±
OUTB2±
OUTC2±
OUTD2±
TMS
TCLK
TDO
TDI
Notes:
5.
6.
Name
Device Configuration and Control Bus Signals
Internal Device Configuration Latches
Analog I/O
JTAG Interface
See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.
See Device Configuration and Control Interface for detailed information on the internal latches.
LVTTL input,
asynchronous,
internal pull-up
LVTTL input
asynchronous,
internal pull-up
LVTTL input
asynchronous,
internal pull-up
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
LVTTL input,
internal pull-down
LVTTL input,
internal pull-down
CML Differential
Output
CML Differential
Output
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
3-State LVTTL
Output
LVTTL Input,
internal pull-up
I/O Characteristics Signal Description
(continued)
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Control Write Enable. The WREN input writes the values of the DATA[4:0] bus into the
latch specified by the address location on the ADDR[3:0] bus.
Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to configure
the device. The WREN input writes the values of the DATA[4:0] bus into the latch specified
by the address location on the ADDR[3:0] bus.
within the device, and the initialization value of the latches upon the assertion of RESET.
Table 3 shows how the latches are mapped in the device.
Control Data Bus. The DATA[4:0] bus is the input data bus used to configure the device.
The WREN input writes the values of the DATA[4:0] bus into the latch specified by address
location on the ADDR[3:0] bus.
and the initialization value of the latches upon the assertion of RESET. Table 3 shows how
the latches are mapped in the device.
Transmit Clock Select.
Transmit PLL Clock Rate Select.
Transmit Bist Disabled.
Differential Serial Output Driver 2 Enable.
Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.
Global Latch Enable.
Force Global Latch Enable.
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as a NO
CONNECT, or GND only.
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a NO
CONNECT, or GND only.
Primary Differential Serial Data Output. The OUTx1± PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-
optic transmitter modules, and must be AC-coupled for PECL-compatible connections.
Secondary Differential Serial Data Output. The OUTx2± PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic
transmitter modules, and must be AC-coupled for PECL-compatible connections.
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for
≥5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock.
Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected.
Test Data In. JTAG data input port.
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Table 2 lists the configuration latches within the device,
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Table 2 lists the configuration latches
CYV15G0403TB
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