cyv15g0104trb Cypress Semiconductor Corporation., cyv15g0104trb Datasheet - Page 20

• Manufacturer Part Number: cyv15g0104trb
• Description: Independent Clock Hotlink Ii Serializer And Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02100 Rev. *B
CYV15G0104TRB AC Electrical Characteristics
PLL Characteristics
t
t
t
t
t
t
CYV15G0104TRB Bus Configuration Write Timing Characteristics Over the Operating Range
t
t
t
CYV15G0104TRB JTAG Test Clock Characteristics Over the Operating Range
f
t
CYV15G0104TRB Device RESET Characteristics Over the Operating Range
t
CYV15G0104TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range
t
t
t
CYV15G0104TRB Transmitter Output PLL Characteristics
t
t
t
CYV15G0104TRB Reclocker Output PLL Characteristics
t
t
Notes:
23. The duty cycle specification is a simultaneous condition with the t
24. TRGCLKA± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
25. While sending BIST data at the corresponding data rate, after 10,000 histogram hits, time referenced to REFCLKB± input.
26. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The
TRGH
TRGL
TRGD
TRGR
TRGF
TRGRX
DATAH
DATAS
WRENP
TCLK
TCLK
RST
B
RISE
FALL
JTGENSD
JTGENHD
TXLOCK
JRGENSD
JRGENHD
Parameter
Parameter
Parameter
cycle cannot be as large as 30%–70%.
TRGCLKA± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLK±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
measurement was recorded after 10,000 histogram hits, time referenced to REFCLKB± of the transmit channel.
[16]
[16]
[16, 17, 18]
[23]
[16, 17, 18]
[24]
[16, 25]
[16, 25]
[16, 26]
[16, 26]
TRGCLKA HIGH Time (TRGRATEA = 1)(Half Rate)
TRGCLKA HIGH Time (TRGRATEA = 0)(Full Rate)
TRGCLKA LOW Time (TRGRATEA = 1)(Half Rate)
TRGCLKA LOW Time (TRGRATEA = 0)(Full Rate)
TRGCLKA Duty Cycle
TRGCLKA Rise Time (20%–80%)
TRGCLKA Fall Time (20%–80%)
TRGCLKA Frequency Referenced to Received Clock Frequency
Bus Configuration Data Hold
Bus Configuration Data Setup
Bus Configuration WREN Pulse Width
JTAG Test Clock Frequency
JTAG Test Clock Period
Device RESET Pulse Width
Bit Time
CML Output Rise Time 20−80% (CML Test Load)
CML Output Fall Time 80−20% (CML Test Load)
Transmit Jitter Generation - SD Data Rate
Transmit Jitter Generation - HD Data Rate
Transmit PLL lock to REFCLKB±
Reclocker Jitter Generation - SD Data Rate
Reclocker Jitter Generation - HD Data Rate
Description
Description
Description
TRGH
and t
(continued)
TRGL
parameters. This means that at faster character rates the TRGCLKA± duty
REFCLKB = 27 MHz
REFCLKB = 148.5 MHz
TRGCLKA = 27 MHz
TRGCLKA = 148.5 MHz
SPDSELx = HIGH
SPDSELx= MID
SPDSELx =LOW
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
Condition
Condition
2.9
2.9
–0.15
CYV15G0104TRB
Min.
Min.
100
660
180
100
180
5.9
5.9
30
10
10
50
50
50
30
Min.
0
[16]
[16]
Typ.
107
200
133
76
+0.15
Max.
5128
1000
1000
Max
270
500
270
500
70
20
2
2
Page 20 of 27
Max.
200
MHz
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
%
%
ps
ps
µs
ps
ps
ps
ps
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