max2991 Maxim Integrated Products, Inc., max2991 Datasheet
![no-image](/images/no-image-200.jpg)
max2991
Available stocks
Related parts for max2991
max2991 Summary of contents
Page 1
... The MAX2991 power-line communication analog front- end (AFE state-of-the-art integrated circuit that delivers high integration and superb performance, while reducing the total system cost. The MAX2991 is the first AFE specifically designed for OFDM (orthogonal fre- quency division multiplexing) modulated signal transmis- sion over power lines ...
Page 2
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver ABSOLUTE MAXIMUM RATINGS V to GND ..........................................................-0.3V to +3.9V DD All Other Inputs/Outputs .......................................-0.3V to +3.9V Continuous Power Dissipation (T = +70NC) A 48-Pin LQFP (derate 25mW/NC above +70NC) ..........1535mW Stresses beyond those ...
Page 3
Power-Line Communications (PLC) Integrated ELECTRICAL CHARACTERISTICS (continued 3.3V 0V -40NC to +85NC, unless otherwise noted. Typical values are GND A PARAMETER SYMBOL RECEIVER (Note 4) Input Impedance Receiver Dynamic Range Lowpass ...
Page 4
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver Tx FILTER TRANSFER FUNCTION (CENELEC -10 -20 -30 -40 -50 - FILTER TRANSFER FUNCTION (FCC -10 -20 -30 -40 -50 -60 -70 50 200 ...
Page 5
Power-Line Communications (PLC) Integrated SPI™ TIMING CHARACTERISTICS (Figure 2) PARAMETER SYMBOL SCLK Frequency SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Low to SCLK Setup t CS Low After SCLK Hold CS High to SCLK Setup t CS ...
Page 6
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver AFE INTERFACE TIMING CHARACTERISTICS (Rx) (Figure 4) PARAMETER SYMBOL RXCLK Frequency RXCLK Clock Period RXCLK Pulse-Width High RXCLK Pulse-Width Low RXCONV Low to RXCLK Setup RXCONV Low After RXCLK Hold t RXCONV Pulse-Width ...
Page 7
Power-Line Communications (PLC) Integrated AFE INTERFACE TIMING CHARACTERISTICS (Tx) (Figure 6) PARAMETER SYMBOL TXCLK Frequency TXCLK Clock Period TXCLK Pulse-Width High TXCLK Pulse-Width Low TXCONV Low to TXCLK Setup t TXCONV Low After TXCLK Hold t TXCONV High to TXCLK ...
Page 8
... Active-High AGC Freeze-Mode Enable. Drive AGCFRZ high to place the AGC adaptation in freeze 13 AGCFRZ mode. Drive AGCFRZ low to allow continuous AGC adaptation. 8 ______________________________________________________________________________________ MAX2991 LQFP FUNCTION inputs together. DD inputs together. DD ...
Page 9
... ADC Reference Voltage Output. Internal 2.0V reference output. Bypass REF with parallel 100nF and 36 REF 10FF capacitors to the ADC ground. Active-Low Shutdown Input. Drive SHDN low to place the MAX2991 into shutdown mode. Drive 37 SHDN SHDN high for normal operation. Receive Bias. RBIASRX is the external resistor connection that sets the bias current for the receive ...
Page 10
... Lowpass Filter Negative Output LPFOUT 46 LPFOUT Lowpass Filter Positive Output Active-Low Reset Input. Drive RST low to place the MAX2991 in reset mode. Leave Rx and Tx clocks 47 RST in free-running mode during a reset. The minimum reset pulse width is 100ns. Connect RST to V for normal operation. ...
Page 11
... ENTX enables the transmitter of the MAX2991 AFE cir- cuit. A logic-high on ENTX powers down the MAX2991 transmitter. ENRX enables the receiver on the MAX2991. A logic- high on ENRX powers down the MAX2991 receiver. The TXCLK signal provides the clock to the MAX2991 AFE transmitter. Apply a 19.2MHz clock at TXCLK to achieve 1 ...
Page 12
... Analog Front-End Transceiver AGC Control Signals (AGCCS) The AGCCS signal controls the AGC circuit of the receive path in the MAX2991. A logic-low on AGCCS sets the gain circuit on the input signal to continuously adapt for maximum sensitivity. A valid preamble detected by the digital PHY raises AGCCS to high. While AGCCS is high, ...
Page 13
Power-Line Communications (PLC) Integrated Table 1. Register Map (continued) REGISTER WIDTH ADDRESS IIR0B2 <15:0> IIR0A1 <15:0> IIR0A2 <15:0> IIR1CONF <8:0> IIR1B0 <15:0> IIR1B1 <15:0> IIR1B2 <15:0> IIR1A1 <15:0> IIR1A2 <15:0> DPTUN1 <11:0> DPTUN2 <11:0> FRZTIME <11:0> Address 0x00: Rx Configuration ...
Page 14
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver Address 0x01: Tx Configuration (TXCONF<15:0>), Default: 0x282B LOCATION BIT NAME (0 = LSB) ENTXBEN 0 PREDRVGAIN 4–1 <3:0> — 5 TXLPFBW<1:0> — 12–8 PREDRDYN 13 TXCONV_EDGE 14 TXDATA_DLY 15 Address 0x03: ...
Page 15
Power-Line Communications (PLC) Integrated Address 0x04: Process Tuner Adjust (PTUN2<13:0>), Default: 0x0000 LOCATION BIT NAME (0 = LSB) PTUNERXADJ 6–0 <6:0> PTUNETXADJ 13–7 <6:0> Address 0x07: AGC Control 3 (AGC3<13:0>), Default: 0x0320 LOCATION BIT NAME (0 = LSB) — 10–0 ...
Page 16
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver Address 0x10: IIR0 A1 Coefficient (IIR0A1<15:0>), Default: 0xCEFF LOCATION BIT NAME (0 = LSB) IIR0_A1<15:0> 15–0 Address 0x11: IIR0 A2 Coefficient (IIR0A2<15:0>), Default: 0x1613 LOCATION BIT NAME (0 = LSB) IIR0_A2<15:0> 15–0 Address ...
Page 17
Power-Line Communications (PLC) Integrated Address 0x16: IIR1 A1 Coefficient (IIR1A1<15:0>), Default: 0xC7F6 LOCATION BIT NAME (0 = LSB) IIR1_A1<15:0> 15–0 Address 0x17: IIR1 A2 Coefficient (IIR1A2<15:0>), Default: 0x1F4D LOCATION BIT NAME (0 = LSB) IIR1_A2<15:0> 15–0 Address 0x18: Process Tuner ...
Page 18
... Figure 8. Interfacing with the MAX2990 Applications Information Programming the Process Tuner Reference Clock The MAX2991 uses a reference clock to tune Rx and Tx filters. In default mode, Rx clock is used as the reference source for the process tuner. Process tuner clock can be set to any one of RXCLK, TXCLK, or REFCLK clock sources. PTUN1< ...
Page 19
... SPI. The SPI frame has 4 command bits labeled C3, C2, C1, and C0. These bits are normally set to 0 when transferring data frames to the DAC. The MAX2991 also responds to other command codes, shown in Table 4, Table 4. Configuration Bits COMMAND BITS ...
Page 20
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver Dynamic Predriver Gain Programming During the Data Transmission During normal data transmission bit used to indicate that a normal data packet is received and bits C2, C1, and C0 ...
Page 21
... Power-Line Communications (PLC) Integrated Table 7. Rx and Tx Filter Adjustment for Different 3dB Frequencies Rx 3dB FREQUENCY Tx 3dB FREQUENCY (kHz) 130 140 146 155 Table 8. IIR Coefficients for CENELEC A Band (MAX2991 Default Mode) COEFFICIENT NAME FLOATING POINT VALUE IIR0B0 IIR0B1 IIR0B2 IIR0A1 IIR0A2 IIR1B0 ...
Page 22
... RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 LQFP Maxim is a registered trademark of Maxim Integrated Products, Inc. REGISTER VALUE 5563 0x15BB 10449 ...