ad8112jstz1 Analog Devices, Inc., ad8112jstz1 Datasheet
ad8112jstz1
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ad8112jstz1 Summary of contents
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... Tel: 781.329.4700 Fax: 781.461.3113 AD8112 SER/PAR 80-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING 40 40 PARALLEL LATCH NO CONNECT 40 8 DECODE 8 × 5:16 DECODERS AD8112 OUTPUT 128 BUFFER SWITCH MATRIX Figure 1. www.analog.com ©2007 Analog Devices, Inc. All rights reserved DATA OUT ...
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AD8112 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics (Serial) .................................................. 5 Timing Characteristics (Parallel) ............................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. ...
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SPECIFICATIONS T = 25° ± 600 Ω, unless otherwise noted Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Gain Flatness Propagation Delay Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential ...
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AD8112 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time Step Switching Transient (Glitch) POWER SUPPLIES Supply Current DYNAMIC PERFORMANCE Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θ JA Conditions 50% update to 1% settling AV outputs ...
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TIMING CHARACTERISTICS (SERIAL) Table 2. Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid, Serial Mode Propagation Delay, UPDATE to ...
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AD8112 TIMING CHARACTERISTICS (PARALLEL) Table 4. Parameter Data Setup Time CLK Pulse Width Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Analog Supply Voltage ( Digital Supply Voltage (DV to DGND) CC Ground Potential Difference (AGND to DGND) Internal Power Dissipation 1 2 Analog Input Voltage Digital Input Voltage Output ...
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AD8112 Table 7. Operation Truth Table CE UPDATE CLK DATA IN DATA OUT Data Data ... D4, N ... A2 Parallel Mode ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 DGND 2 AGND 3 IN08 4 AGND 5 IN09 6 AGND 7 IN10 8 AGND 9 IN11 10 AGND 11 IN12 12 AGND 13 IN13 14 AGND 15 IN14 16 ...
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AD8112 Pin No. 21, 22, 26, 30, 34, 38 50, 46, 42 52, 48, 44 23, 25, 27, 29, 31, 33, 35, 37 ...
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I/O SCHEMATICS V CC ESD INPUT ESD AV EE Figure 7. Analog Input V CC ESD ESD AV EE Figure 8. Analog Output V CC ESD 20kΩ RESET ESD DGND Figure 9. Reset Input OUTPUT Rev Page 11 ...
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AD8112 TYPICAL PERFORMANCE CHARACTERISTICS 3 0 –3 –6 0.01 0.1 1 FREQUENCY (MHz) Figure 12. Small-Signal Bandwidth ± 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0.1 1 FREQUENCY (MHz) Figure 13. Small-Signal Gain Flatness, V ...
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FREQUENCY (MHz) Figure 18. Large-Signal Gain Flatness ± –40 ALL HOSTILE –50 –60 –70 –80 –90 –100 0.1 1 FREQUENCY (MHz) Figure 19. Crosstalk vs. Frequency, ...
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AD8112 300 250 200 V = ±12V 150 600Ω L 100 SERIES RESISTANCE (Ω) Figure 24. Capacitive Load vs. Series Resistance for Less than 30% Overshoot 10k 1k 100 10 ...
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FREQUENCY (MHz) Figure 30. PSRR vs. Frequency 160 140 120 100 100 1k 10k 100k FREQUENCY (Hz) ...
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AD8112 500mV/DIV 100ns/DIV Figure 36. Large-Signal Pulse Response, V UPDATE 2V/DIV V OUT INPUT 0 100ns/DIV Figure 37. Switching Time ± UPDATE 1V/DIV OUTPUT 20mV/DIV 100ns/DIV Figure 38. Switching Transient ± ...
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THEORY OF OPERATION The AD8112 has a gain of +2 and is a crosspoint array with eight outputs, each of which can be connected to any one of 16 inputs. Organized by output row, 16 switchable transconductance stages are connected ...
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AD8112 When calculating on-chip power dissipation necessary to include the rms current being delivered to the load multiplied by the rms voltage drop on the AD8112 output devices. The dissipation of the on-chip, 4 kΩ feedback resistor network ...
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APPLICATION NOTES The AD8112 has two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 80 bits is provided to update the entire matrix. The serial data needs to be prefixed with ...
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AD8112 low. This technique should be used when programming the device for the first time after power-up when using parallel programming. POWER-ON RESET When powering up the AD8112 usually desirable to have the outputs in the disabled state. ...
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Video signals usually use 75 Ω transmission lines that need to be terminated with this value of resistance at each end. When such a source is delivered to one of the AD8112 inputs, the high input impedance does not properly ...
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AD8112 IN00 TO IN15 1kΩ TERM IN16 TO IN31 1kΩ TERM IN32 TO IN47 1kΩ TERM IN48 TO IN63 1kΩ TERM IN64 TO IN79 1kΩ TERM IN80 TO IN95 1kΩ ...
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MULTICHANNEL VIDEO AND AUDIO The video specifications of the AD8112 make it an ideal candidate for creating composite video crosspoint switches. These can be made quite dense by taking advantage of the AD8112’s high level of integration and the fact ...
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AD8112 All these sources of crosstalk are vector quantities; therefore the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can reduce the ...
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For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN07 in the middle) are programmed to connect to IN00. OUT07 is programmed to connect to IN15 (not in ...
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AD8112 PCB LAYOUT Extreme care must be exercised to minimize additional cross- talk generated by the system circuit board(s). The areas that must be carefully designed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8112 is ...
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DV CC DGND AGND P1-1 P1-2 P1-3 P1-4 P1-5 P1-6 P1 JUMPER + 0.1µF 10µF 0.1µF 10µF 58 INPUT 00 IN00 57, 59 75Ω AGND 60 INPUT 01 IN01 61 75Ω AGND ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD8112JSTZ 1 0°C to 70°C 1 AD8112-EVALZ Pb-free part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 0.20 0.09 7° 3.5° ...