mc13109 Freescale Semiconductor, Inc, mc13109 Datasheet - Page 21

• Manufacturer Part Number: mc13109
• Description: Universal Cordless Telephone Subsystem
• Manufacturer: Freescale Semiconductor, Inc

“Clk Out” Divider Programming
and can be used to drive a microprocessor, thereby reducing
the number of crystals required. Figure 23 shows the
relationship between the crystal frequency and the clock
output for different divider values. Figure 24 shows the “Clk
Out” register bit values.
Gain Control Register
Carrier Detect threshold. Operation of these latch bits are
explained in Figures 26 and 27.
Frequency
10.24 MHz
12.00 MHz
11.15 MHz
MOTOROLA ANALOG IC DEVICE DATA
The “Clk Out” pin is derived from the 2nd local oscillator
Crystal
Crystal
The gain control register contains bits which control the
Volume Control
Clk Out
Bit #1
Bit #3
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 24. Clock Output Divider
Figure 23. Clock Output Values
5.120 MHz
5.575 MHz
6.000 MHz
2
3.413 MHz
3.717 MHz
4.000 MHz
Clk Out
Volume Control
Clock Output Divider
Bit #0
0
1
0
1
3
Bit #2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2.560 MHz
2.788 MHz
3.000 MHz
5
Divider Value
Clk Out
Volume Control
10
Figure 25. Volume Control
2.048 MHz
2.230 MHz
2.400 MHz
2
3
5
10
Bit #1
MC13109
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MPU “Clk Out“ Power–Up Default Divider Value
provides an MPU clock of about 1.0 MHz after initial
power–up. The reason for choosing this relatively low clock
frequency after intial power–up is that some microprocessors
that operate down to a 2.0 V power supply have a maximum
clock frequency fo 1.0 MHz. After initial power–up, the MPU
can change the clock divider value to set the clock to the
desired operating frequency. Special care has been taken in
the design of the clock divider to ensure that the transition
between one clock divider value and another is “smooth”
(i.e., there will be no narrow clock pulses to disturb the MPU).
MPU “Clk Out” Radiated Noise on Circuit Board
microprocessor has the potential to radiate noise which can
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 k
resistor is included on–chip in–series with the “Clk Out” output
driver. A small capacitor can be connected to the “Clk Out” line
on the PCB to form a single pole low pass filter. This filter will
significantly reduce noise radiated from the “Clk Out” line.
Volume Control
steps from –14 dB to +16 dB. The power–up default value is
0 dB.
The power–up default divider value is “divide by 10”. This
The clock line running between the MC13109 and the
The volume control can be programmed in 2.0 dB gain
Volume Control
Bit #0
Figure 26. Gain Control Latch Bits
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MSB
5–Bit CD Threshold Control
Control #
Volume
10
12
13
14
15
11
0
1
2
3
4
5
6
7
8
9
Gain/Attenuation
Amount
– 8.0 dB
– 6.0 dB
– 4.0 dB
– 2.0 dB
LSB
–14 dB
–12 dB
–10 dB
2.0 dB
4.0 dB
6.0 dB
8.0 dB
10 dB
12 dB
14 dB
16 dB
0 dB
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