mc13202 Freescale Semiconductor, Inc, mc13202 Datasheet
mc13202
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mc13202 Summary of contents
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... GHz Low Power Transceiver ® for the IEEE 802.15.4 Standard 1 Introduction The MC13202 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13202 contains a complete 802.15.4 physical layer (PHY) modem designed for the ® IEEE 802.15.4 Standard which supports peer-to-peer, star, and mesh networking ...
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... MC13202 Reference Manual, (MC13202RM). Applications include, but are not limited to, the following: • Residential and commercial automation — Lighting control — Security — Access control — Heating, ventilation, air-conditioning (HVAC) — Automated meter reading (AMR) • Industrial Control — Asset tracking and monitoring — ...
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... Meets lead-free requirements 2.1 Software Features Freescale provides a wide range of software functionality to complement the MC13202 hardware. There are three levels of application solutions: 1. Simple proprietary wireless connectivity. 2. User networks built on the 802.15.4 MAC standard. 3. ZigBee-compliant network stack. ...
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... Supports star, mesh and tree networks • Advanced Encryption Standard (AES) 128-bit security 3 Block Diagrams Figure 1 shows a simplified block diagram of the MC13202 which is an 802.15.4 Standard compatible transceiver that provides the functions required in the physical layer (PHY) specification. 1st IF Mix MHz LNA RFIN_P ...
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... Figure 3 shows the packet structure of the MC13202. Payloads 125 bytes are supported. The MC13202 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of the data. ...
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... Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 µs period after the packet preamble and stored in RAM. If the MC13202 is in packet mode, the data is processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt. ...
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... SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency. If the MC13202 is in packet mode, data is processed as an entire packet. The data are first loaded into the TX buffer. The MCU then requests that the MC13202 transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted ...
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... If the supply voltage is produced by a switching DC-DC converter, ripple should be less than 100 mV peak-to-peak. 8 Table 1. Maximum Ratings Symbol V BATT, Symbol DDINT BATT, V DDINT SPI P max f ref MC13202 Technical Data, Rev. 1.2 Value V -0.3 to 3.6 DDINT Vin -0 0.3) DDINT P 10 max T 125 J T -55 to 125 stg Min Typ Max 2.0 2.7 3.4 2.405 - 2.480 -40 ...
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... °C, unless otherwise noted) DDINT A Symbol ) DDINT I leakage I CCH I CCD I CCI I CCT I CCR ) (All digital inputs MC13202 Technical Data, Rev. 1.2 Min Typ Max Unit - 0.2 1.0 µA - 1.0 6.0 µ 102 µA - 500 800 µ ± ...
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... SPI Register 12 programmed to 0x00FF which sets output power to maximum 2 ° MHz, unless otherwise noted.) A ref Symbol SENS per SENS max = 2 ° MHz, unless otherwise noted.) A ref Symbol P out EVM MC13202 Technical Data, Rev. 1.2 Min Typ Max Unit - -92 - dBm - -92 -87 dBm - 10 - dBm - ...
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... Table 6. Digital Timing Specifications SPI timing parameters are referenced to Min 125 50 50 250 6.8nH LDB212G4005C-001 3.9nH C2 10pF Figure 6. RF Parametric Evaluation Circuit MC13202 Technical Data, Rev. 1.2 Figure 8. Typ Max Not Mounted ANT1 1.0pF F_Antenna ...
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... SPI bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13202. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK ...
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... The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13202 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in ...
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... In this context, a write is data written to the MC13202 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). ...
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... Off Mode and all internal information is lost from RAM and SPI registers. When high, IC goes to IDLE Mode, with SPI in default state. MC13202 Technical Data, Rev. 1.2 Functionality When used with internal T/R switch, this is a bi-directional RF port for the internal LNA and PA ...
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... Digital regulated supply bypass. Digital interface supply & digital regulator input. Connect to Battery. General Purpose Input/Output 5. General Purpose Input/Output 6. General Purpose Input/Output 7. Crystal Reference oscillator input. MC13202 Technical Data, Rev. 1.2 Functionality See Footnote 2 See Footnote 2 See Footnote 2 See Footnote 2 See Footnote 3 See Footnote 2 Open drain device ...
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... Connect to directly VDDLO1 and VDDLO2 externally and to PAO± through a bias network. Note: Do not use this pin to supply circuitry external to the chip. External paddle / flag ground. MC13202 Technical Data, Rev. 1.2 Functionality Connect to 16 MHz crystal and load capacitor. Decouple to ground. Decouple to ground. ...
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... RFIN_M 2 RFIN_P 3 CT_Bias PAO_P 6 PAO_M GPIO4 MC13202 Figure 10. Pin Connections (Top View) MC13202 Technical Data, Rev. 1 GPIO6 23 GPIO5 22 VDDINT 21 VDDD 20 IRQ MISO 17 MOSI 16 Freescale Semiconductor ...
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... Whether or not a frequency trim step will be performed in production Freescale requires the use MHz crystal with a <9 pF load capacitance. The MC13202 does not contain a reference divider MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance ...
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... Initial tolerance for the internal trim capacitance is approximately ±15%. Since the MC13202 contains an on-chip reference frequency trim capability possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a board-by-board basis. Individual trimming of each board in a production environment allows use of the lowest cost crystal, but requires that each board go through a trimming procedure ...
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... If the MCU is also going to be used in low power modes, be sure that all unused IO are programmed properly for low power operation (typically best case is as outputs in the low state). The MC13202 is commonly used with the Freescale MC9S08GT/GB 8-bit devices. For these MCUs: — ...
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... Transceiver RF Configurations and External Connections The MC13202 radio has features that allow for a flexible as well as low cost RF interface: • Programmable output power — 0 dBm nominal output power, programmable from -27 dBm to +4 dBm typical • ...
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... The CT_Bias is connected to the balun center-tap providing the proper DC bias voltage to the balun depending TX. Freescale Semiconductor RX SW ITCH PA2 PA2 ENABLE CT_Bias Generator CT_Bias CONTROL PA1 FROM TX PSM PA1 ENABLE Figure 12. RF Interface Pins MC13202/03 RFIN_P (PAO_P) Balun L1 RFIN_M (PAO_M) CT_Bias Bypass PAO_P PAO_M MC13202 Technical Data, Rev. 1.2 RX LNA SIGNAL RX ENABLE 23 ...
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... L1 form a matching network. Inductors L2 and L3 are ac-coupled to ground to form a frequency trap. For the transmit side, the TX antenna is connected to the differential PAO outputs, and inductors L4 and L5 provide DC-biasing to VDDA but are ac-isolated. CT_Bias is not required or used. 24 MC13202 Technical Data, Rev. 1.2 Freescale Semiconductor ...
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... ass M C 1320 2/ ias ( tl ass RX Antenna L1 TX Antenna Bypass MC13202 Technical Data, Rev. 1 RFIN_P (PAO_P) RFIN_M (PAO_M) MC13202/03 VDDA Bypass L4 L5 CT_Bias PAO_P PAO_M ...
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... Register 07 with the RF interface control bits Register r/w r/w r/w r 0x0C00 Figure 15. Control_B Register 07 Model Operation”. The use of CT_Bias pin in Dual Port Mode is controlled MC13202 Technical Data, Rev. 1.2 0x07 r/w r Section 9.1.1, “Single Port Freescale Semiconductor ...
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... Dual Port Mode selected where RFIN_M and RFIN_P are inputs only and PAO_P and PAO_N are separate outputs. (This is default operation). RF_switch_mode CT_Bias_inv MC13202 Technical Data, Rev. 1.2 Operation Table 11. Table 11. This bit only Section 9.1.1, “Single Section 9.1.2, “Dual Port CT_Bias Hi ...
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... Figure 16 shows a typical single port RF application in which part count is minimized and a printed copper F antenna is used for low cost. Only the RFIN port of the MC13202 is required because the differential port is bi-directional and uses the on-chip T/R switch. Matching to near 50 Ohms is accomplished with L1, L2, L3, and the traces on the PCB ...
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... DETAIL N CORNER CONFIGURATION OPTION 4 1.6 BACKSIDE 1.5 PIN 1 INDEX 0.475 0.425 0.25 R 0.15 DETAIL M BACKSIDE PIN 1 INDEX OPTION (Case 1311-03, Issue E) MC13202 Technical Data, Rev. 1.2 0.1 1.00 1.0 0.05 0.75 0.8 (0.25) 0.05 (0.5) 0.00 C SEATING PLANE DETAIL G VIEW ROTATED 90° CLOCKWISE 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N ...
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... P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MC13202 Rev. 1.2 05/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...