mc13202 Freescale Semiconductor, Inc, mc13202 Datasheet - Page 14

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mc13202

Manufacturer Part Number
mc13202
Description
Mc13203 2.4ghz Rf Transceiver For Zigbee Applications
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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6.2.2
Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13202 requires that a complete
SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion
of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the
transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and
identifies the access as being a read or write operation. In this context, a write is data written to the
MC13202 and a read is data written to the SPI master. The following SPI bursts will be either the write
data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).
Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13202
never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to
a larger number depending on the type of access. The number of payload bytes sent will always be an even
integer. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the
MC13202 Reference Manual, (MC13202RM) for more details on SPI registers and transaction types.
An example SPI read transaction with a 2-byte payload is shown in
14
SPI Transaction Operation
S P IC L K
C E
M IS O
M O S I
C lo c k B u rst
Figure 9. SPI Read Transaction Diagram
MC13202 Technical Data, Rev. 1.2
H e a d e r
V a lid
V a lid
R e a d d a ta
Figure
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9.
Freescale Semiconductor

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