z86131 ZiLOG Semiconductor, z86131 Datasheet - Page 9

• Manufacturer Part Number: z86131
• Description: Ntsc Line 21 Decoder
• Manufacturer: ZiLOG Semiconductor

ZiLOG
RREF (Pin 10).
be 10 kOhms, ±2%.
Power Supply
V
and may range between 4.75 to 5.25 Volts with respect to
the V
PIN DESCRIPTIONS (Z86130/131 ONLY)
Inputs
VIDEO (Pin 7).
(nom), band limited to 600 kHz. The circuit operates with
signal variation between 0.7–1.4V p-p. The polarity is sync
tips negative. This signal pin should be AC coupled through
a 0.1 µF capacitor and driven by a source impedance of 470
ohms or less.
HIN/XIN (Pin 5).
modes. When XTAL mode has been selected (see HIN de-
scription below) the horizontal sync signal is generated on
the chip using an external 32.768-kHz crystal circuit, as il-
lustrated below. This circuit must be connected between pin
5 and 3.
When HIN mode has been selected a Horizontal Sync input
signal at CMOS level must be supplied to pin 5. When the
device is used in VIDEO LOCK mode, this signal pulls the
on-chip V
DS007200-TVX0199
DD
Crystal Type: 32.768 kHz, CL=12.5pF
(Pin 12).
SS
Z86130/131
pins.
CO
within the proper range. The circuit uses the
The voltage on this pin is nominally 5.0 Volts
Pin 5
Pin 3
Composite NTSC video input, 1.0V p-p
Reference setting resistor. Resistor must
Figure 6. XTAL Circuit
This pin can function in two different
Epson, C-001R 32.768 kHz or
Fox, NC26, NC28 or equivalent
Series Resistance < 35 kOhms
32.768KHz
Y1
470K
R2
(18 kOhms typ)
R1
22M
C2
C1
10pF
20pF
P R E L I M I N A R Y
V
pins for the analog and digital circuits. They are normally
tied to system ground.
Note: The recommended printed circuit pattern for implement-
frequency of this signal which must be within +3% F
can be of either polarity. When used in the H LOCK mode,
the V
HPOL bit of the H Position register can be set to operate
with either polarity of input signal (usually the H Flyback
signal).
SMS (Pin 6).
When this input is at a CMOS High state (1) the Serial Con-
trol Port operates in the SPI mode. When the input is Low
(0), the Serial Control Port operates in the I
In SPI mode, the SEN pin must be tied High. (See Reset
Operation section, below.)
SEN (Pin 4).
the Serial Control Port. When this pin is Low (0), the SPI
port is disabled and the SDO pin is in the high-impedance
state. Transitions on the SCK and SDA pins are ignored.
SPI mode operation is enabled when SMS is High (1).
SCK (Pin 15).
master control device. In I
is expected to be within I
imum clock frequency is 10 MHz.
I
Address 29h and the Slave Write Address 28h. Tying this
pin High selects the alternate Slave Address but it is not
available in the current version.
H SEL (Pin 2).
signal. Tying pin 2 High selects the XTAL mode. The
32.768-kHz crystal circuit must be connected between pins
5 & 3. Tying pin 2 Low selects HIN mode operation. The
appropriate Horizontal Sync signal must be supplied to
pin 5.
Reset Operation.
in the Low (0) state, the part is in the Reset state. Therefore,
in the I
When SPI mode is used, if three wire operation is desired,
both SMS and SEN can be tied together and used as the
2
SS
C SEL (Pin 1).
(Pins 1, 11).
CO
2
ing the power connection and critical components is in
the Application Information section, page 58.
C mode the SEN pin can be used as an NReset input.
phase locks to the rising edge of this signal. The
Enable signal for the SPI mode operation of
Mode select pin for the Serial Control Port.
Input pin for serial clock signal from the
It selects the source of the Horizontal Sync
Tying this pin Low selects the Slave Read
These pins are the lowest potential power
When the SMS and SEN pins are both
2
2
C limits. In SPI mode, the max-
C mode operation the clock rate
NTSC Line 21 Decoder
Z86129/130/131
2
C slave mode.
h
but
9