hmp8156a Intersil Corporation, hmp8156a Datasheet - Page 23

• Manufacturer Part Number: hmp8156a
• Description: Ntsc/pal Video Encoder
• Manufacturer: Intersil Corporation

NUMBER
NUMBER
BIT
BIT
7-0
7-4
2
1
0
Field Detect
Window Size Low
Half Line Count
Reset Value
VSYNC Edge
Select
FIELD Detect
Select
Field Detect
Window Size High
FUNCTION
FUNCTION
23
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1X clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are config-
ured as inputs.
0 = leading edge
1 = trailing edge
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are config-
ured as inputs.
0 = odd field
1 = even field
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size
value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
TABLE 29. FIELD CONTROL REGISTER 1
TABLE 30. FIELD CONTROL REGISTER 2
HMP8154, HMP8156A
SUB ADDRESS = 26
SUB ADDRESS = 27
DESCRIPTION
DESCRIPTION
H
H
November 4, 2005
RESET
RESET
00000
STATE
STATE
80
0
0
0
B
B
B
H
4343.4
B