hmp8112 Harris Corporation, hmp8112 Datasheet - Page 20

• Manufacturer Part Number: hmp8112
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

NUMBER
NUMBER
NUMBER
NUMBER
3 - 0
7 - 0
7 - 6
4 - 0
BIT
BIT
BIT
BIT
1
0
7
6
5
4
5
Vertical Pixel Siting
Not Used
Software Reset
Black Screen
Line Locked Flag
Standard Error Flag This flag when set (‘1’) indicates that the Standard detected does not match the one se-
Not Used
Reserved Read
Only
Reserved Read
Only
Lost HSYNC
Control
Reserved Read
Only
FUNCTION
FUNCTION
FUNCTION
FUNCTION
TABLE 28. OUTPUT FORMAT CONTROL REGISTER (Continued)
TABLE 29. SOFTWARE RESET AND VIDEO STATUS REGISTER
When this bit is cleared (‘0’) the chrominance pixels have a 1/2 line pixel offset from their
associated luminance pixel in a 4:2:2 subsampled scheme. When this bit is set (‘1’) the
pixel siting is line aligned with the luminance pixels in a 4:2:2 subsampled scheme. The
bit is cleared by a RESET.
Write Ignored, Read 0’s
When this bit is set to 1, the entire device except the I
exactly like the RESET input. The software reset will initialize all register bits to their reset
state as well as place the PLLs back at the power-up state. Once set this bit is self clear-
ing after only 4 CLK periods. This bit is cleared on power-up by the external RESET pin.
This flag when set (‘1’) will set the output video to black when a lost vertical sync has
been detect. This flag is cleared after a RESET.
This flag when set (‘1’) indicates that the Line Locked-Phase Locked Loop has locked to
the video data. The state of this flag is reflected on the LOCKED output pin. This flag is
cleared after a RESET of Software Reset.
lected in the Video Input Control Register. The standard is checked against a line count
and if the line count is significantly different than the expected value then this flag is trig-
gered. The state of this flag is reflected on the STANDARD_ERROR output pin. This flag
is cleared after a RESET or Software Reset.
Write ignored, Read 0’s.
This register is reserved for future use. This register will read all zero’s and is write ig-
nored.
This register is reserved for future use. This register will read all zero’s and is write ig-
nored.
This bit controls when the PLL will declare lost horizontal sync, leave track mode and re-
turn to acquisition to acquire a new HSYNC reference. This bit should be used with
VCR’s with extremely gross headswitch errors. When this bit is cleared, lost line lock is
declared after 12 missing horizontal syncs. When this bit is set, lost line lock is declared
after one missing horizontal sync and the line lock PLL will reacquire the first HSYNC is
detects. This bit is cleared by RESET.
This register is reserved for future use. This register will read all zero’s and is write ignored.
DESTINATION ADDRESS = 16
DESTINATION ADDRESS = 17
DESTINATION ADDRESS = 18
DESTINATION ADDRESS = 19
TABLE 30. RESERVED
TABLE 31. RESERVED
HMP8112
20
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
2
C bus is reset to a known state
0000 0000
Read Only
Read Only
Read Only
XXXX XX
0 0000
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
00
0
0
0
X
B
B
B
B
B
B