cat93c86late13 Catalyst Semiconductor, cat93c86late13 Datasheet - Page 4
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cat93c86late13
Manufacturer Part Number
cat93c86late13
Description
16k-bit Microwire Serial Eeprom
Manufacturer
Catalyst Semiconductor
Datasheet
1.CAT93C86LATE13.pdf
(13 pages)
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
DEVICE OPERATION
The CAT93C86 is a 16,384-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The CAT93C86 can be organized as either regis-
ters of 16 bits or 8 bits. When organized as X16, seven
13-bit instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
14-bit instructions control the reading, writing and erase
operations of the device. The CAT93C86 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations).
Note: The Write, Erase, Write all and Erase all instructions
require PE=1. If PE is left floating, 93C86 is in Program
POWER-UP TIMING
A.C. TEST CONDITIONS
Doc. No. 1091, Rev. O
CAT93C86
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Symbol
t
t
PUR
PUW
PUR
and t
PUW
are the delays required from the time V
(1)(2)
Parameter
Power-up to Read Operation
Power-up to Write Operation
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
0.5V
CC
CC
to 0.7V
CC
CC
is stable until the specified operation can be initiated.
4
Enabled mode. For Write Enable and Write Disable
instruction PE=don’t care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86 will
come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the device will automatically increment to the next address
and shift out the next data word in a sequential READ
mode. As long as CS is continuously asserted and SK
continues to toggle, the device will keep incrementing to
the next address automatically until it reaches to the end
of the address space, then loops back to address 0. In
the sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C86 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
4.5V ≤ V
4.5V ≤ V
1.8V ≤ V
1.8V ≤ V
Max
1
1
CC
CC
CC
CC
≤ 5.5V
≤ 5.5V
≤ 4.5V
≤ 4.5V
CSMIN
. The falling edge of CS will start the
PD0
or t
Units
ms
ms
PD1
).