at42qt1060 ATMEL Corporation, at42qt1060 Datasheet
at42qt1060
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at42qt1060 Summary of contents
Page 1
... Power: – 1.8V to 5.5V • Package: – 28-pin MLF RoHS compliant IC • Signal Processing: – Self-calibration – auto drift compensation – noise filtering – Adjacent Key Suppression™ • Applications: – Mobile appliances ™ QTouch 6-channel Sensor IC AT42QT1060 9505E–AT42–02/09 ...
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... Pinout and Schematic 1.1 Pinout Configuration 1.2 Pin Descriptions Table 1-1. Pin AT42QT1060 SNS1K 2 SNS2K 3 VDD QT1060 4 VSS 5 IO5 IO6 6 SNS3K Pin Listing Name Type Description SNS1K capacitor and to key ...
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... SNS0K capacitor and to key I Input only O Output only, push-pull OD Open drain output AT42QT1060 If Unused, Connect To... Leave open and set as output Leave open and set as output Leave open and set as output Leave open Resistor to Vdd or Vss only in standalone mode Resistor to Vdd or ...
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... Torex (XC6215 series) • Seiko (S817 series) • BCDSemi (AP2121 series) Re Figure 1-1 • Section 3.1 on page • Section 3.2 on page • Section 3.5 on page • Section 5.4 on page • Section 3.3 on page AT42QT1060 4 VDD 100nF CB1 SNS5K 25 RST SNS5 SNS4K 6 SNS4 IO6 5 SNS3K IO5 ...
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... Overview 2.1 Introduction The AT42QT1060 (QT1060 digital burst mode charge-transfer (QT driver designed specifically for mobile phone applications. The device can sense from two to six keys four keys can be disabled by not installing their respective sense capacitors (Cs). It also has up to seven configurable input/output lines, with Pulse Width Modulation (PWM) for LED driving ...
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... Adjacent Key Suppression (AKS) Technology The device includes Atmel’s patented Adjacent Key Suppression (AKS) technology, to allow the use of tightly spaced keys on a keypad with no loss of selectability by the user. AT42QT1060 6 Section 6.12 on page 20) which can be written to via I 2 C-compatible communication ...
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... Keys outside the group may be in detect simultaneously. Figure Figure 1-1 on page Table 6-1 on page 17). Create a guard channel by removing that key from the key AT42QT1060 2.9). 4) signals when there is a change in state in Table 6-1 on page 2 C-compatible Section 6.15 17). ...
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... Detect Threshold The device detects a touch when the signal has crossed a threshold level and remained there for a specified number of counts (see key-by-key basis using the key threshold I AT42QT1060 8 Section 2.11.3). 17). In addition, the guard channel needs to be included within the AKS mask with the Guard Channel Example Section 6 ...
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... For details of how to select these resistors see the Application Note QTAN0002, Secrets of a Successful QTouch Touch Technology area of Atmel’s website, www.atmel.com. 9505E–AT42–02/09 Section 6.20 on page Section 6.22 on page 23). The chosen Cs value should never be ™ Design, downloadable from the AT42QT1060 23). The fast DI will not be 9 ...
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... To assist with transient regulator stability problems, the QT1060 waits 500 µs any time it wakes up from a sleep state (i.e. in SLEEP and LP modes) before acquiring, to allow Vdd to fully stabilize. AT42QT1060 10 for the power supply range. If the power supply fluctuates slowly Figure 1-1 on page 4 for suggested regulator manufacturers ...
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... The only exception to this rule is for generating START and STOP conditions. 9505E–AT42–02/09 2 -compatible Interface Bus I C Device 1 Device 2 SDA SCL 2 -compatible Bus Specifications I C AT42QT1060 2 -compatible bus protocol is available from -compatible bus as shown Vdd Device 3 Device n R1 Unit 7-bit 100 kHz 4 µ ...
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... SDA low in the ninth SCL (ACK) cycle. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The most significant bit of the address byte is transmitted first. The address sent by the host must be consistent with that selected with the option jumpers. Figure 4-5. AT42QT1060 12 Data Transfer SDA SCL ...
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... Note that several data bytes can be transmitted Data Packet Format Data MSB 1 2 SLA+R/W Packet Transmission Addr MSB Addr LSB R/W ACK SLA+R/W AT42QT1060 Data LSB ACK STOP or Data Byte Next Data Byte Data MSB Data LSB ACK ...
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... There is one preset I 5.3 Data Read/Write 5.3.1 Writing Data to the Device The sequence of events required to write data to the device is shown next. Table 5-1. Key S SLA+W A AT42QT1060 14 2 C-compatible hardware and transfers with the chip may be corrupted. 2 C-compatible address of 0x12. This is not changeable. Host to Device S SLA+W A MemAddress ...
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... SLA+W A MemAddress Data 2 Data 1 A the next address. Each time a data byte is transmitted, the device automatically increments the internal address. The device continues to return data bytes until the host responds with a NACK. STOP condition. AT42QT1060 Device to Host SLA+R A Data ...
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... The termination resistors commonly range from 1 k k rise times on SDA and SCL meet the I Standalone mode can be enabled by connecting SDA to Vss and SCL to Vdd. See information. AT42QT1060 16 2 C-compatible master and slave devices can only drive these lines low or 2 C-compatible specifications (1 µ ...
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... Key 5 R/W Res'd IO6 IO5 R/W Res'd IO6 IO5 R/W Res'd IO6 IO5 R/W Res'd IO6 IO5 R/W MSB R/W MSB AT42QT1060 Bit 4 Bit 3 Bit 2 Minor Version number Minor version number Reserved Key4 Key3 Key2 Input 4 Input 3 Input 2 Reserved Res'd Res'd Res'd IO4 IO3 IO2 Key 4 ...
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... MINOR VERSION NUMBER: this is the 8-bit minor firmware revision number (0x00). 6.5 Address 4: Detection Status Table 6-5. Address 4 CAL indicates that the QT1060 is currently calibrating. KEY0 – 5: bits indicate which keys are in detection, if any; touched keys report as 1, untouched or disabled keys report as 0. AT42QT1060 18 Bit 7 Bit 6 Bit Chip ID b7 ...
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... INPUT 5 INPUT 4 Calibrate Writing a nonzero value forces a calibration Reset Writing a nonzero value forces a reset Drift Option 9). Normal drifting is also carried out but at a slower rate compared to AT42QT1060 INPUT 3 INPUT 2 INPUT ...
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... Address 22: LP Mode Table 6-12. Address 22 LP Mode: this 8-bit value determines the number intervals between key measurements. Longer intervals between measurements yield lower power consumption at the expense of slower response to touch. AT42QT1060 20 Positive Recalibration Delay POSITIVE RECALIBRATION DELAY NTHR Keys 0 – 5 ...
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... IO6 IO5 Section 6.24 on page 24 for I/O register precedence and example usage. (all IO's are set as outputs (0x7F), when using the standalone mode) Key Mask CAL Reserved KEY5 AT42QT1060 IO4 IO3 IO2 IO1 sets the pin as an output C-compatible mode) ...
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... Address 28: Active Level Mask Table 6-18. Address 28 IO0 – 6 (Active Level Mask): these bits control the active logic level for the IOs that are configured as outputs. A output is active low. See Default: 0 (all IOs are active low output) AT42QT1060 22 AKS Mask Reserved Reserved KEY5 ...
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... Detection Integrator MSB DETECTION INTEGRATOR PWM Level MSB Key Signal LSB OF KEY SIGNAL FOR KEY 0 MSB OF KEY SIGNAL FOR KEY 0 LSB/MSB OF KEY SIGNAL FOR KEYS 1 – 5 AT42QT1060 IO4 IO3 IO2 IO1 PWM LEVEL ...
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... Note don’t care (can AT42QT1060 24 Reference Data LSB OF REFERENCE DATA FOR KEY 0 MSB OF REFERENCE DATA FOR KEY 0 LSB/MSB OF REFERENCE DATA FOR KEYS 1 – 5 gives the order of priority for the settings in the mask inputs/outputs. The settings in ...
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... Tune the sensitivity of the keys by adjusting the value of the sampling capacitor, Cs and the negative threshold (NTHR) [Address 16 – 21: NTHR] 9505E–AT42–02/09 AT42QT1060 To Set Up I/O Lines Determine the direction of the I /O lines. If any lines are unused , set them to be outputs and leave them unconnected . ...
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... Vdd = 3.3V 10nF, load = 5 pF default sleep recommended range, unless otherwise noted Parameter Description Vil Low input logic level Vih High input logic level Vol Low output voltage Voh High output voltage Iil Input leakage current Ar Acquisition resolution AT42QT1060 26 -0.5 to +6V ±10 mA infinite infinite -0.6V to (Vdd + 0.6) Volts o - + +125 +1.8V to 5.5V ±25 mV ...
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... Minimum Typical Maximum DI setting LP mode + (DI setting x – ms) 162 180 198 – <230 – – – 100 5 – – AT42QT1060 1.8V 1.8 1.1 403 373 360 351 348 346 345 Units Notes ms Under host control Modulated kHz spread-spectrum (chirp) Can be longer if burst is ms very long ...
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... D2 R 0.20 b BOTTOM VIEW The terminal # Laser-marked Feature. Note: 2325 Orchard Parkway San Jose, CA 95131 R AT42QT1060 28 The central pad on the underside of the MLF chip should be connected to ground. Do not run any tracks underneath the body of the chip, only ground ...
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... QT1060 -MMU Chip LTCODE Traceability Code Description 28-pin MLF RoHS compliant IC MSL Rating Peak Body Temperature MSL3 AT42QT1060 Chip Traceability Code Program week code number 1-52 where 2... then using the underscore A = 27... Specifications o 260 C IPC/JEDEC J-STD-020 ...
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... Revision History Revision Number Revision A – September 2008 Revision B – October 2008 Revision C – November 2008 Revision D – December 2008 Revision E – February 2009 AT42QT1060 30 History Initial Release for code revision 3.0 Minor amendments to burst length limitations Minor amendments to improve clarity ...
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... Notes 9505E–AT42–02/09 AT42QT1060 31 ...
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... Suppression , AKS , QTouch , QT and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be registered trademarks or trademarks of others. International Atmel Asia Atmel Europe Unit 01-05 & 16, 19/F Le Krebs BEA Tower, Millennium City 5 8, Rue Jean-Pierre Timbaud ...