qt401 Quantum Research Group, qt401 Datasheet - Page 7

• Manufacturer Part Number: qt401
• Description: Qslide? Touch Slider Ic
• Manufacturer: Quantum Research Group

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3 Serial Communications
The serial interface is a SPI slave-only mode type which is
compatible with multi-drop operation, ie the MISO pin will float
after a shift operation to allow other SPI devices (master or
slave) to talk over the same bus. There should be one
dedicated /SS line for each QT401 from the host controller.
A DRDY (‘data ready’) line is used to indicate to the host
controller when it is possible to talk to the QT401.
3.1 Power-up Timing Delay
Immediately after power-up, DRDY floats for approximately
20ms, then goes low. The device requires ~525ms thereafter
before DRDY goes high again, indicating that the device has
calibrated and is able to communicate.
3.2 SPI Timing
The SPI interface is a five-wire slave-only type; timing is
found in Figure 3-1, page 6.
The phase clocking is as follows:
The host can shift data to and from the QT on the same cycle
(overlapping commands). Due to the nature of SPI, the return
data from a command or action is always one SPI cycle
behind.
An acquisition burst always happens about 920µs after /SS
goes high after coming out of Sleep mode .
3.2.1 /SS Line
/SS acts as a framing signal for SPI data clocking under host
control. See Figure 3-1.
After a shift operation /SS must go high again, a minimum of
35µs after the last clock edge on CLK. The device
automatically goes into sleep state during this interval, and
wakes again after /SS rises. If /SS is simply held low after a
shift operation, the device will remain in sleep state up to the
maximum time shown in Figure 3-1. When /SS is raised,
another acquisition burst is triggered.
lQ
7.
8.
9.
Data out changes on:
Data Ready DRDY:
Input data read on:
Bit length & order:
If there are LEDs or LED wiring near the electrode or its
wiring (ie for backlighting of the key), bypass the LED
wiring to ground on both its ends.
Use a voltage regulator just for the QT401 to eliminate
noise coupling from other switching sources via Vdd.
Make sure the regulator’s transient load stability provides
for a stable voltage just before each burst commences.
If Mains noise (50/60 Hz noise) is present, use the Sync
feature to suppress it if possible (see Section 1.1).
Slave Select /SS:
Clock rate:
Clock idle:
High
Falling edge of CLK from host
Rising edge of CLK from host
Negative level frame from host
Low from QT inhibits host
8 bits, MSB shifts first
5kHz min, 40kHz max
7
If /SS is held high all the time, the device will burst in a
free-running mode at a ~17Hz rate. In this mode a valid
position result can be obtained quickly on demand, and/or
one of the two OUT pins can be used to wake the host. This
rate depends on the burst length which in turn depends on
the value of each Cs and load capacitance Cx. Smaller
values of Cs or higher values of Cx will make this rate faster.
Dummy /SS Burst Triggers: In order to force a single burst,
a dummy ‘command’ can be sent to the device by pulsing /SS
low for 10µs to 10ms; this will trigger a burst on the rising
edge of /SS without requiring an actual SPI transmission.
DRDY will fall within 56µs of /SS rising again, and then a
burst will occur 1mS later (while DRDY stays low).
After the burst completes, DRDY will rise again to indicate
that the host can get the results.
Note: Pin /SS clamps to Vss for 250ns after coming out of
sleep state as a diagnostic pulse. To prevent a possible pin
drive conflict, /SS should either be driven by the host as an
open-drain pull-high drive (e.g. with a 100K pullup resistor), or
there should be a ~1K resistor placed in series with the /SS
pin.
3.2.2 DRDY Line
The DRDY line acts primarily as a way to inhibit the host from
clocking to the QT401 when the QT401 is busy. It also acts to
signal to the host when fresh data is available after a burst.
The host should not attempt to clock data to the QT401 when
DRDY is low, or the data will be ignored or cause a framing
error.
On power-up, DRDY will first float for about 20ms, then pull
low for ~525ms until the initial calibration cycle has
completed, then drive high to indicate completion of
calibration. The device will be ready to communicate in
typically under 600ms (with Cs1 = Cs2 = 100nF).
While DRDY is a push-pull output, it does float for ~400µs
after power-up and after wake from Sleep mode. It is
desirable to use a pulldown resistor on DRDY to prevent false
signalling back to the host controller; see Figure 1-1 and
Section 1.3.
3.2.3 MISO / MOSI Data Lines
MISO and MOSI shift on the falling edge of each CLK pulse.
The data should be clocked in on the rising edge of CLK. This
applies to both the host and the QT401. The data path follows
a circular buffer, with data being mutually transferred from
host to QT, and QT to host, at the same time. However the
return data from the QT is always the standard response byte
regardless of the command.
The setup and hold times should be observed per Figure 3-1.
3.2.4 Sleep Mode
Please refer to Figure 3-1, page 6.
The device always enters low-power sleep mode after an SPI
transmission (Figure 3-1), at or before about 35µs after the
last rising edge of CLK. Coincident with the sleep mode, the
device will lower DRDY. If another immediate acquisition
burst is desired, /SS should be raised again at least 35 µs
after the last rising edge of CLK. To prolong the sleep state, it
is only necessary to raise /SS after an even longer duration.
In sleep mode, the device consumes only a few microamps of
current. The average current can be controlled by the host, by
QT401 R10.04/0505