pga370 ETC-unknow, pga370 Datasheet - Page 40

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Pentium
40
Table 17. System Bus AC Specifications (CMOS Signal Group)
Table 18. System Bus AC Specifications (Reset Conditions)
Table 19. System Bus AC Specifications (APIC Clock and APIC I/O)
Table 20. Platform Power-On Timings
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
NOTE: 1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
NOTES:
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after V
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150
T45: Valid Time Before VTT_PWRGD
T46: Valid Time Before PWRGOOD
T47: RESET# Inactive to Valid Outputs
T48: RESET# Inactive to Drive Signals
T14: CMOS Input Pulse Width, except
T15: PWRGOOD Inactive Pulse Width
T16: Reset Configuration Signals
T17: Reset Configuration Signals
T21: PICCLK Frequency
T22: PICCLK Period
T23: PICCLK High Time
T24: PICCLK Low Time
T25: PICCLK Rise Time
T26: PICCLK Fall Time
T27: PICD[1:0] Setup Time
T28: PICD[1:0] Hold Time
T29a: PICD[1:0] Valid Delay (Rising Edge)
T29b: PICD[1:0] Valid Delay (Falling Edge)
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
PWRGOOD
(A[14:5]#, BR0#, INIT#) Setup Time
(A[14:5]#, BR0#, INIT#) Hold Time
T# Parameter
T# Parameter
T# Parameter
T# Parameter
CC CORE
2
, V
Min
TT
1.0
2.0
1
4
Min
10
, V
2
30.0
10.5
10.5
0.25
0.25
Min
Min
2.0
5.0
2.5
1.5
1.5
CC CMOS
4
2
Max
, and BCLK become stable.
Max
Max
20
500.0
Max
33.3
12.0
3.0
3.0
8.7
load pulled up to 1.5 V.
1
BCLK
BCLK
Unit
BCLKs
BCLKs
mS
mS
BCLKs
BCLKs
Unit
Unit
1, 2, 3, 4
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2, 3
Figure
Figure
Figure
14
14
14
14
11,
11
13
13
Figure
10,
10,
14
12
12
9
9
9
9
9
11
11
Before deassertion
of RESET#
After clock that
deasserts RESET#
Active and
Inactive states
(0.7V - 1.7V)
(1.7V - 0.7V)
@ > 1.7V
@ < 0.7V
Notes
Notes
Notes
Notes
4, 5, 6
4, 5, 6
Datasheet
1
1
1
1
5
4
4