adt7420ucpz-rl7 Analog Devices, Inc., adt7420ucpz-rl7 Datasheet - Page 4

• Manufacturer Part Number: adt7420ucpz-rl7
• Manufacturer: Analog Devices, Inc.

ADT7420
I
T
(10% to 90% of V
Table 2.
Parameter
SERIAL INTERFACE
1
2
Timing Diagram
2
Sample tested during initial release to ensure compliance.
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
A
C TIMING SPECIFICATIONS
SCL Frequency
SCL High Pulse Width, t
SCL Low Pulse Width, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
Setup Time (Stop Condition), t
Data Hold Time, t
Bus-Free Time (Between Stop and Start Condition), t
= −40°C to +150°C, V
SDA
SCL
DD
1, 2
P
HD:DAT
t
) and timed from a voltage level of 1.6 V.
BUF
SU:DAT
F
R
S
(Master)
LOW
DD
HIGH
t
HD:STA
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
HD:STA
SU:STO
t
SU:STA
LOW
t
R
t
HD:DAT
Figure 2. Serial Interface Timing Diagram
BUF
t
HIGH
t
F
t
SU:DAT
Rev. PrB | Page 4 of 24
Min
0
0.6
1.3
0.6
0.6
0.25
0.35
0.6
0
1.3
Typ
Max
400
0.3
0.3
S
t
SU:STA
Unit
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
t
HD:STA
Preliminary Technical Data
Test Conditions/Comments
See Figure 2
After this period, the first clock is generated
Relevant for repeated start condition
V
V
DD
DD
≥ 3.0 V
< 3.0 V
t
SU:STO
R
) = fall time (t
P
F
) = 5 ns