w83628g Winbond Electronics Corp America, w83628g Datasheet - Page 18

• Manufacturer Part Number: w83628g
• Description: Pci-to-isa Bridge , Kit With W83629d.
• Manufacturer: Winbond Electronics Corp America

8.9 WISA_STS-ISA BRIDGE ERROR STATUS REGISTER
Address Offset:
Default Value:
Attribute:
Bit 7:3
Bit 2
Bit 1
Bit 0
8.10 WISA_FADC-ISA BRIDGE FAST DECODERS CONTROL REGISTER
Address Offset:
Default Value:
Attribute:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8.11 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 0 MASK CONTROL REGISTER
Address Offset:
Default Value:
Attribute:
This register is used to mask address bits(A7~A0) for fast address decoder # 0, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 0.
8.12 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 1 MASK CONTROL REGISTER
Address Offset:
Default Value:
Attribute:
This register is used to mask address bits(A7~A0) for fast address decoder # 1, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 1.
Reserved.
IOCHK# Pin State.
Enable/Disable Fast I/O Address Decoder # 7.
Enable/Disable Fast I/O Address Decoder # 6.
Enable/Disable Fast I/O Address Decoder # 5.
Enable/Disable Fast I/O Address Decoder # 4.
Enable/Disable Fast I/O Address Decoder # 3.
Enable/Disable Fast I/O Address Decoder # 2.
Enable/Disable Fast I/O Address Decoder # 1.
Enable/Disable Fast I/O Address Decoder # 0.
This bit reflects the inverse state of IOCHK# pin on the ISA bus.
Reserved.
Byte Lane Error.
This bit is set if the ISA bridge detects an illegal byte lane combination for a
PCI I/O cycles.
42h
00h
Read/Write
50h
00h
Read/Write
58h
00h
Read/Write
59h
00h
Read/Write
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W83628F & W83629D