w83629d Winbond Electronics Corp America, w83629d Datasheet - Page 15

• Manufacturer Part Number: w83629d
• Description: Pci To Isa Bridge Set
• Manufacturer: Winbond Electronics Corp America

Bit 3
Bit 2
Bit 1
Bit 0
8.4 PCISTS-PCI STATUS REGISTER
Address Offset:
Default Value:
Attribute:
This register shows status information for PCI bus related events.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10:9
Bit 8
Bit 7
Parity Error Response(Not supported).
Hardwired to zero.
Bus Master Enable.
Hardwired to one. The ISA bridge Bus Masters are always supported to generate a
PCI Bus master cycle.
Memory Space Enable.
Hardwired to one. The ISA bridge Memory space is always enabled.
I/O Space Enable.
Hardwired to one. The ISA bridge I/O space is always enabled.
Detected Parity Error.
Hardwired to zero. The ISA bridge does not check bus parity.
Signaled System Error.
This bit is set when ISA bridge asserts SERR# on PCI bus.
Received Master Abort Status.
This bit is set when the ISA bridge is target aborted as a master on the PCI bus.
Software sets this bit to 0 by writing a 1 to it.
Received Target Abort Status.
This bit is set when the ISA bridge target aborts a PCI transaction as a target.
Software sets this bit to 0 by writing a 1 to it.
Signaled Target Abort Status.
This bit is set when the ISA bridge signals a target abort for a PCI transaction.
Software sets this bit to 0 by writing a 1 to it.
DEVSEL# Timing. This 2 bits always return a 01b(medium decode).
Data Parity Detected(Not supported).
Hardwired to zero.
Fast Back-to-Back(Not supported).
Hardwired to zero.
06-07h
0200h
Read/Write
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W83628F & W83629D
Publication Release Date: May 18, 2005
Revision A1