w83697 Winbond Electronics Corp America, w83697 Datasheet - Page 57

• Manufacturer Part Number: w83697
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
TABLE 4-2 WORD LENGTH DEFINITION
4.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
DLS1
is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the
bit is reset, an odd number of logic 1's are sent or checked.
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position
as the transmitter will be detected.
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
0
0
1
1
checked.
checked.
each serial character.
DLS0
7
0
1
0
1
6
5
4
DATA LENGTH
3
5 bits
6 bits
7 bits
8 bits
2
1
0
- 48 -
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RBR Data ready (RDR)
RX FIFO Error Indication (RFEI)
Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70