w83977f Winbond Electronics Corp America, w83977f Datasheet - Page 68

• Manufacturer Part Number: w83977f
• Description: Plug & Play 1.0a Compliant
• Manufacturer: Winbond Electronics Corp America

Bit 1:
Bit 0:
4.2.3.2 IR FIFO Control Register (UFR):
Legacy IR:
This register is used to control FIFO functions of the IR.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example,
TABLE: FIFO TRIGGER LEVEL
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit will be
Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before
Legacy IR RXFTL1
Advanced
Reset Value
Mode
IR
BIT 7
UFR bit 0 = 1.
cleared to logical 0 by itself after being set to logical 1.
cleared to a logical 0 by itself after being set to logical 1.
other bits of UFR can be programmed.
0
0
1
1
if the interrupt active level is set as 4 bytes and there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO.
TXEMP_I - Transmitter Empty.
Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Cleared to 0 when this
register is read.
RXTH_I - Receiver Threshold Interrupt.
Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold
level; or (2) RBR time-out occurs if the receiver buffer register has valid data and below
the threshold level. Cleared to 0 when RBR is less than threshold level after reading
RBR.
RXFTL1
(MSB)
(MSB)
Bit 7
0
BIT 6
0
1
0
1
RXFTL0
RXFTL0
(LSB)
(LSB)
Bit 6
0
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
TXFTL1
(MSB)
Bit 5
0
0
- 56 -
TXFTL0
(LSB)
Bit 4
0
0
01
04
08
14
W83977F/ W83977AF
Bit 3
0
0
0
Publication Release Date: March 1998
TXF_RST RXF_RST EN_FIFO
TXF_RST RXF_RST EN_FIFO
Bit 2
0
PRELIMINARY
Bit 1
0
Revision 0.58
Bit 0
0