w83977eg Winbond Electronics Corp America, w83977eg Datasheet - Page 11

• Manufacturer Part Number: w83977eg
• Description: Winbond Isa I/o W83977ef W83977eg
• Manufacturer: Winbond Electronics Corp America

4. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O 6t
I/O 8t
I/O 8
I/O 12t
I/O 12
I/O 16u
I/OD 16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor
I/O 24t
OUT 8t
OUT 12t - TTL level output pin with 12 mA source-sink capability
OD 12
OD 24
IN t
IN c
IN cu
IN cs
IN ts
IN tsu
4.1
A0−A10
A11-A14
A15
D0−D5
D6−D7
IOR#
IOW#
AEN
IOCHRDY
MR
DACK0#
GP16
(WDTO)
P15
SYMBOL
Host Interface
- TTL level bi-directional pin with 6 mA source-sink capability
- TTL level bi-directional pin with 8 mA source-sink capability
- CMOS level bi-directional pin with 8 mA source-sink capability
- TTL level bi-directional pin with 12 mA source-sink capability
- CMOS level bi-directional pin with 12 mA source-sink capability
- CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 8 mA source-sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
- TTL level input pin
- CMOS level input pin
- CMOS level input pin with internal pull-up resitor
- CMOS level Schmitt-triggered input pin
- TTL level Schmitt-triggered input pin
- TTL level Schmitt-triggered input pin with internal pull-up resistor
109-114
116-117
74-84
86-89
105
106
107
108
118
119
PIN
91
I/O
I/O
I/O
I/O
OD
IN
IN
IN
IN
IN
I/O
IN
IN
IN
tsu
12t
12t
12t
12t
ts
ts
ts
ts
24
t
t
t
System address bus bits 0-10
System address bus bits 11-14
System address bus bit 15
System data bus bits 0-5
System data bus bits 6-7
CPU I/O read signal
CPU I/O write signal
System address bus enable
In EPP Mode, this pin is the IO Channel Ready output to
extend the host read/write cycle.
Master Reset; Active high; MR is low during normal
operations.
DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00,
default)
General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)
Alternate function from GP16: Watch dog timer output
KBC P15 I/O port. (CR2C bit 5_4 = 10)
W83977EF-AW/W83977EG-AW
-9-
FUNCTION
Publication Release Date: Apr. 2006
Revision 1.2