sak-xc2766x-96f66l-ac Infineon Technologies Corporation, sak-xc2766x-96f66l-ac Datasheet - Page 101

• Manufacturer Part Number: sak-xc2766x-96f66l-ac
• Description: 16/32-bit Single-chip Microcontroller With 32-bit Performance
• Manufacturer: Infineon Technologies Corporation

XC2766X
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Bus Cycle Control with the READY Input
The duration of an external bus cycle can be controlled by the external circuit using the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
An asynchronous READY signal puts no timing constraints on the input signal but incurs
a minimum of one waitstate due to the additional synchronization stage. The minimum
duration of an asynchronous READY signal for safe synchronization is one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next bus cycle is controlled by READY, an active READY signal must be disabled
before the first valid sample point in the next bus cycle. This sample point depends on
the programmed phases of the next cycle.
Data Sheet
99
V2.0, 2008-03