sak-xc2766x-96f66l-ac Infineon Technologies Corporation, sak-xc2766x-96f66l-ac Datasheet - Page 50

• Manufacturer Part Number: sak-xc2766x-96f66l-ac
• Description: 16/32-bit Single-chip Microcontroller With 32-bit Performance
• Manufacturer: Infineon Technologies Corporation

Preliminary
3.8
The GPT12E unit is a very flexible multifunctional timer/counter structure which can be
used for many different timing tasks such as event timing and counting, pulse width and
duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers organized in two separate modules,
GPT1 and GPT2. Each timer in each module may either operate independently in a
number of different modes or be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation: Timer, Gated Timer, Counter, and Incremental
Interface Mode. In Timer Mode, the input clock for a timer is derived from the system
clock and divided by a programmable prescaler. Counter Mode allows timer clocking in
reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes each timer has one associated port pin (TxIN
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The counting direction (up/down) for each timer can be programmed by software or
altered dynamically by an external signal on a port pin (TxEUD
position tracking.
In Incremental Interface Mode the GPT1 timers
incremental position sensor signals A and B through their respective inputs TxIN and
TxEUD. Direction and counting signals are internally derived from these two input
signals, so that the contents of the respective timer Tx corresponds to the sensor
position. The third position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to the basic operating modes, T2 may be configured as reload or capture
register for timer T3. A timer used as capture or reload register is stopped. The contents
of timer T3 is captured into T2 in response to a signal at the associated input pin (TxIN).
Timer T3 is reloaded with the contents of T2, triggered either by an external signal or a
selectable state transition of its toggle latch T3OTL.
1) Exception: Timer T4 is not connected to pins.
Data Sheet
General Purpose Timer (GPT12E) Unit
48
1)
can be directly connected to the
1)
XC2000 Family Derivatives
) which serves as a gate or clock
Functional Description
1)
), e.g. to facilitate
V2.0, 2008-03
XC2766X