ssm2518 Analog Devices, Inc., ssm2518 Datasheet
ssm2518
Available stocks
Related parts for ssm2518
ssm2518 Summary of contents
Page 1
... Using the SSM2518, audio data can be transmitted to the amplifier over a standard digital audio serial interface, thereby significantly reducing the effect of noise sources such as GSM interference or other digital signals on the transmitted audio ...
Page 2
... SSM2518 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Performance Specifications......................................................... 5 Power Supply Requirements ....................................................... 6 Digital Input/Output.................................................................... 6 Digital Interpolation Filter .......................................................... 6 Digital Timing............................................................................... 7 Absolute Maximum Ratings ....................................................... 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 14 Power Supplies ...
Page 3
... Changes to Table 1, Supply Current Parameter ............................5 Changes to Table 3, Input Voltage Parameter................................6 Changes to Table 7 ............................................................................8 Added Figure 5 and Table 9, Renumbered Sequentially ............10 Changes to Power-Down Modes Section.....................................14 Changes to Master and Bit Clock Section....................................14 Changes to Sample Rate Detection Section.................................17 10/11—Revision 0: Initial Version Rev Page SSM2518 ...
Page 4
... SSM2518 FUNCTIONAL BLOCK DIAGRAM LRCLK BCLK SDATA SD DVDD SA_MOD PVDD POWER-ON RESET FULL BRIDGE Σ-∆ VOLUME CLASS-D DAC CONTROL MODULATOR DRC FULL BRIDGE CLOCKING POWER CONTROL MCLK SDA SCL ADDR Figure 1. Rev Page Data Sheet GND OUTL+ ...
Page 5
... Ω μH, LP_MODE = 0, volume A L Min Typ 2 2.5 1.42 1.8 1.3 1.7 0.75 0.94 0.4 0.45 0.275 0. 0.04 0.03 108 280 2 100 4.7 4.4 3.8 4 100 3.0 1 kHz 0.25 S 2.5 100 100 SSM2518 Max Unit kHz μ μA nA μV μ ...
Page 6
... SSM2518 POWER SUPPLY REQUIREMENTS Table 2. Parameter PVDD DVDD DIGITAL INPUT/OUTPUT Table 3. Parameter INPUT VOLTAGE High ( Low ( INPUT LEAKAGE CURRENT High ( Low ( MCLK INPUT LEAKAGE CURRENT High ( Low ( INPUT CAPACITANCE DIGITAL INTERPOLATION FILTER Table 4. Parameter PASS BAND − ...
Page 7
... SIS Figure 2. Serial Input Port Timing t DS SCH t t SCLH SCS t SCR t t SCLL SCF 2 Figure Port Timing Rev Page mode (MCS = b0010) S mode (MCS = b0001 LIH t SIS MSB LSB t t SIH SIH t SCH t BFT STOP CONDITION SSM2518 ...
Page 8
... SSM2518 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 6. Parameter PVDD Supply Voltage DVDD Supply Voltage Input Voltage (ADDR, MCLK, BCLK, LRCLK, SDATA, SAMOD Pins) Input Voltage (SD, SDA, and SCL Pins) ESD Susceptibility Storage Temperature Range ...
Page 9
... V to 3.6 V Digital and Analog Power. Power-Down Control, Active Low Clock Data. Serial Audio Interface Master Clock Word Clock Bit Clock Serial Data. 2 Standalone/I C Mode Select. High = standalone mode, low = Address Select. Rev Page SSM2518 2 C mode. ...
Page 10
... P 20 PVDD input output, I/O is input/output, and P is power. PIN 1 INDICATOR OUTL OUTR+ OUTL– OUTR– SSM2518 ADDR TOP VIEW SDA 4 12 DVDD (Not to Scale) SCL 5 11 SAMOD NOTES 1. CONNECT THE EXPOSED PAD TO GND. Figure 5. LFCSP Pin Configuration ...
Page 11
... MCLK = 256 × 8Ω, 33µH L 0.01 0.1 1 OUTPUT POWER (W) GAIN = 3.6V f MCLK = 256 × 4Ω, 15µH L 0.01 0.1 1 OUTPUT POWER (W) PVDD = 5V GAIN = 5V f MCLK = 256 × 4Ω, 15µH L 100 1k 10k FREQUENCY (Hz) Figure 11. THD + N vs. Frequency, PVDD = SSM2518 2.5V 3.6V 5.0V 10 2.5V 3.6V 5.0V 10 0.25W 0.5W 1.0W 100k = 4 Ω L ...
Page 12
... SSM2518 100 PVDD = 3.6V GAIN = 3.6V f MCLK = 256 × 8Ω, 33µ 0.1 0.01 10 100 1k FREQUENCY (Hz) Figure 12. THD + N vs. Frequency, PVDD = 3 100 PVDD = 2.5V GAIN = 3.6V f MCLK = 256 × 8Ω, 33µ 0.1 0.01 10 100 1k FREQUENCY (Hz) Figure 13. THD + N vs. Frequency, PVDD = 2 DAC_LPM = 1 AMP_LPM = 1 DVDD = 1 ...
Page 13
... L 1kHz 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 100 5V 3. 0.4 0.8 1.2 1.6 2.0 2.4 COMBINED OUTPUT POWER, BOTH CHANNELS (W) Figure 22. Efficiency vs. Output Power into 8 Ω 0 PVDD = 5V PVDD = 2.5V PVDD = 3.6V 10 100 1k 10k FREQUENCY (Hz) Figure 23. PSRR vs. Frequency SSM2518 1% 5% 10% 4.5 5 Ω 8Ω + 33µΗ L 2.8 3.2 100k ...
Page 14
... PVDD or DVDD is substantially below the nominal operating threshold. This circuit simplifies supply sequencing during initial power-on. The circuit also monitors the power supplies to the SSM2518. If the supply voltages fall below the nominal operating threshold, this circuit stops the output and issues a reset. This ensures that no damage occurs due to low voltage operation and that no pops can occur under nearly any power removal condition ...
Page 15
... MCLK pin to serve as the internal bit clock as well. In this case, tie the BCLK pin to ground. Once the SSM2518 has entered its power-down state possible to gate the clocks to conserve system power. However, a valid master clock must be present for the audio amplifier to operate ...
Page 16
... PROCESSOR 1.35V TO 5.5V 2.2kΩ SYSTEM MICROCONTROLLER *OPTIONAL FOR APPLICATIONS WITH >20cm SPEAKER CABLE. PVDD 2.5V TO 5.5V DVDD 1.62V TO 3.6V 100nF 100nF 4.7µF BCLK LRCLK SDATA MCLK SSM2518 2.2kΩ SCL SDA SD SAMOD ADDR GND Figure 24. Typical Application Circuit Using I Rev Page FB1 OUTL+ C1 470pF FB2 OUTL– ...
Page 17
... The control points between these regions can be set using the DRC control registers (Register 0x0A through Register 0x12) using the variable names (CT, ET, and so forth) as shown on the plot axes in Figure 25. Each element can be individually enabled using the LIM_EN, COMP_EN, EXP_EN, and NG_EN bits in Rev Page SSM2518 SMAX ...
Page 18
... To enable the de-emphasis filter, set DEEMP_EN (Bit 4 of Register 0x07). ANALOG GAIN The analog gain of the SSM2518 (Bit 5 of Register 0x07). Each gain setting is designed to match the scaling needed for a specified PVDD voltage so that the digital full-scale values correspond to the clipping points of the amplifier at that voltage ...
Page 19
... If the autorecovery feature is disabled or the maximum number 2 C bit is set of attempts has been reached, the amplifier remains shut down until a software reset or manual fault recovery attempt occurs. The manual fault recovery is triggered by setting the write-only bit, MRCV (Bit 4 of Register 0x08). Rev Page SSM2518 ...
Page 20
... SSM2518 DIGITAL AUDIO FORMATS STEREO MODE SAI = 0 2 SDATA_FMT = 0 (I S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit) BCLK LRCLK SDATA I2S LEFT CHANNEL BCLKs SDATA LJ RIGHT CHANNEL BCLKs SDATA RJ TDM, 50% DUTY CYCLE MODE SAI = 1 (2 slots slots slots), 4 (16 slots) ...
Page 21
... CHANNEL BCLKs Figure 29. Multichannel PCM Modes ANY # BCLKs MONO CHANNEL BCLKs MONO CHANNEL BCLKs MONO CHANNEL BCLKs Figure 30. Mono PCM Modes Rev Page SSM2518 32/24/16 BCLKs CHANNEL BCLKs BCLKs CHANNEL BCLKs ...
Page 22
... SDA line is not pulled low on the ninth clock pulse of SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register acknowledge is issued by the SSM2518, and the part returns to the idle condition Read and Write Operations Figure 33 shows the timing of a single word write operation ...
Page 23
... Rev Page ACK FRAME 2 SUBADDRESS BYTE FRAME 4 DATA BYTE 2 ACK BY DATA BYTE 1 STOP SLAVE (8 BITS) BIT DATA- ACK BY STOP WORD 2 SLAVE BIT ACK BY DATA ACK BY STOP SLAVE BYTE 1 MASTER BIT ACK BY DATA- ACK BY STOP WORD 1 SLAVE MASTER BIT SSM2518 ACK STOP BY MASTER ...
Page 24
... SSM2518 MCLK Frequency Settings Table 11. MCS Bit Field Setting: MCLK, Ratio, and Frequency Input Setting 0 Setting 1 1 Sample Rate b0000 b0001 8 kHz Ratio 256 × f 512 × MCLK 2.048 MHz 4.096 MHz 11.025 kHz Ratio 256 × f 512 × MCLK 2 ...
Page 25
... AR_TIME RESERVED AMP_LPM [7:0] RESERVED PRE_VOL LIM_EN COMP_EN EXP_EN [7:0] PEAK_ATT [7:0] DRC_LT [7:0] DRC_ET [7:0] DRC_SMAX [7:0] DRC_ATT [7:0] HDT_NOR [7:0] RESERVED DRC_POST_G [7:0] RESERVED Rev Page SSM2518 Bit 3 Bit 2 Bit 1 Bit 0 SPWDN EDGE ASR FS SLOT_WIDTH BCLK_EDGE RESERVED CH_SEL_L M_MUTE MAX_AR ARCV DAC_LPM R_PWDN L_PWDN APWDN_EN 0x99 RW ...
Page 26
... SSM2518 REGISTER (REG_MAP) DETAILS SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL REGISTER Address: 0x00, Reset: 0x05, Name: Reset_Power_Control Table 13. Bit Descriptions for Reset_Power_Control Bits Bit Name Settings 7 S_RST 6 RESERVED 5 NO_BCLK [4:1] MCS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 ...
Page 27
... The low EMI operation modes reduce the edge speed, lowering EMI and power efficiency. No edge rate control Low EMI Lower EMI Lowest EMI Automatic Sample Rate Detection. 0 Automatic detection enabled 1 Manual sample rate selection given by FS field, Bits[1:0] of Register 0x02 Rev Page SSM2518 Reset Access 0x00 RW 0x0 RW 0x0 RW ...
Page 28
... SSM2518 SERIAL AUDIO INTERFACE AND SAMPLE RATE CONTROL REGISTER Address: 0x02, Reset: 0x02, Name: Serial_Interface_Sample_Rate_Control Table 15. Bit Descriptions for Serial_Interface_Sample_Rate_Control Bits Bit Name Settings 7 RESERVED [6:5] SDATA_FMT [4:2] SAI 000 001 010 011 100 101 110 111 [1: Description Reserved. ...
Page 29
... TDM Slot Width. Required only for TDM modes. 32 BCLK cycles per slot 24 BCLK cycles per slot 16 BCLK cycles per slot Reserved BCLK Active Edge. 0 Rising BCLK edge used 1 Falling BCLK edge used Reserved. Rev Page SSM2518 Reset Access 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 ...
Page 30
... SSM2518 CHANNEL MAPPING CONTROL REGISTER Address: 0x04, Reset: 0x10, Name: Channel_Mapping_Control Table 17. Bit Descriptions for Channel_Mapping_Control Bits Bit Name Settings [7:4] CH_SEL_R 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] CH_SEL_L 0000 0001 Description Right Channel Select ...
Page 31
... Channel 13 Channel 14 Channel 15 Description Left Channel Volume Control. Adjusts the digital gain in 0.375 dB increments. +24 dB +23.625 dB +23.35 dB +22.875 dB +22.5 dB +22.125 dB … +0.375 −0.375 dB −0.750 dB … −70.875 dB −71.25 dB Mute Rev Page SSM2518 Reset Access Reset Access 0x40 RW ...
Page 32
... SSM2518 RIGHT CHANNEL VOLUME CONTROL REGISTER Address: 0x06, Reset: 0x40, Name: Right_Volume_Control Table 19. Bit Descriptions for Right_Volume_Control Bits Bit Name Settings [7:0] R_VOL 00000000 00000001 00000010 00000011 00000100 00000101 … 00111111 01000000 01000001 01000010 … 11111101 11111110 11111111 Description Right Channel Volume Control. Adjusts the digital gain in 0.375 dB increments ...
Page 33
... Right Channel Soft Mute. 0 Normal operation 1 Right channel muted Left Channel Soft Mute. 0 Normal operation 1 Left channel muted Master Mute Control. This bit soft mutes both channels. 0 Normal operation 1 Master mute Rev Page SSM2518 Reset Access 0x1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 ...
Page 34
... SSM2518 FAULT CONTROL 1 REGISTER Address: 0x08, Reset: 0x0C, Name: Fault_Control_1 Table 21. Bit Descriptions for Fault_Control_1 Bits Bit Name Settings 7 OC_L 6 OC_R MRCV [3:2] MAX_AR [1:0] ARCV Description Left Channel Overcurrent Fault. Read only. 0 Normal operation 1 Left channel overcurrent fault Right Channel Overcurrent Fault ...
Page 35
... Left channel powered down Automatic Power-Down Enable. Automatic power-down automatically puts the low power state when 2048 consecutive zero input samples have been received. 0 Automatic power-down disabled 1 Automatic power-down enabled Rev Page SSM2518 Reset Access 0x2 RW 0x0 RW 0x1 RW 0x1 ...
Page 36
... SSM2518 DRC CONTROL 1 REGISTER Address: 0x0A, Reset: 0x7C, Name: DRC_Control_1 Table 23. Bit Descriptions for DRC_Control_1 Bits Bit Name Settings 7 RESERVED 6 PRE_VOL 5 LIM_EN 4 COMP_EN 3 EXP_EN 2 NG_EN [1:0] DRC_EN Description Reserved. DRC Placement. This determines the placement of the DRC block in the signal chain. When placed before the volume control, the thresholds are relative to the input signal ...
Page 37
... Description DRC Peak Detector Attack Time 0.09 ms 0.19 ms 0.37 ms 0. 192 ms 384 ms 768 ms 1.536 sec DRC Peak Detector Release Time 1 Rev Page SSM2518 Reset Access 0x5 RW 0xB RW ...
Page 38
... SSM2518 Bits Bit Name Settings 1000 1001 1010 1011 1100 1101 1110 1111 DRC CONTROL 3 REGISTER Address: 0x0C, Reset: 0x57, Name: DRC_Control_3 Table 25. Bit Descriptions for DRC_Control_3 Bits Bit Name Settings [7:4] DRC_LT 0000 0001 0010 0011 0100 0101 0110 0111 1000 ...
Page 39
... Description DRC Compressor Lower Threshold Setting. Relative to input. −4 dB −6 dB −8 dB −10 dB −12 dB −14 dB −16 dB −18 dB −20 dB −22 dB −24 dB −26 dB −28 dB −30 dB −32 dB −34 dB Rev Page SSM2518 Reset Access 0x7 RW ...
Page 40
... SSM2518 DRC CONTROL 4 REGISTER Address: 0x0D, Reset: 0x89, Name: DRC_Control_4 Table 26. Bit Descriptions for DRC_Control_4 Bits Bit Name Settings [7:4] DRC_ET 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRC_NT 0000 0001 0010 0011 ...
Page 41
... Description −87 dB −90 dB −93 dB −96 dB Description DRC Limiter Threshold Setting. Relative to input −1 dB −2 dB −3 dB −4 dB −5 dB −6 dB −7 dB −8 dB −10 dB −12 dB −14 dB −16 dB −18 dB −20 dB −22 dB Rev Page SSM2518 Reset Access Reset Access 0x8 RW ...
Page 42
... SSM2518 Bits Bit Name Settings [3:0] DRC_SMIN 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DRC CONTROL 6 REGISTER Address: 0x0F, Reset: 0x77, Name: DRC_Control_6 Table 28. Bit Descriptions for DRC_Control_6 Bits Bit Name Settings [7:4] DRC_ATT ...
Page 43
... DRC Decay Time. Used to smooth the gain curve at the thresholds (knees) of each DRC function 1 192 ms 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Rev Page SSM2518 Reset Access 0x7 RW ...
Page 44
... SSM2518 DRC CONTROL 7 REGISTER Address: 0x10, Reset: 0x26, Name: DRC_Control_7 Table 29. Bit Descriptions for DRC_Control_7 Bits Bit Name Settings [7:4] HDT_NOR 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] HDT_NG 0000 0001 0010 0011 ...
Page 45
... DRC function to compensate for the overall reduction of system gain due to the DRC. +21 dB +18 dB + −3 dB −6 dB −9 dB −12 dB −15 dB −18 dB −21 dB −24 dB Reserved. Rev Page SSM2518 Reset Access Reset Access 0x0 RW 0x7 RW 0x0 RW ...
Page 46
... SSM2518 DRC CONTROL 9 REGISTER Address: 0x12, Reset: 0x07, Name: DRC_Control_9 Table 31. Bit Descriptions for DRC_Control_9 Bits Bit Name Settings [7:4] RESERVED [3:0] RMS_TAV 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Reserved. DRC RMS Detector Averaging Time. This is the averaging time for the rms level that is compared to the DRC thresholds ...
Page 47
... Body, Very Very Thin Quad (CP-20-10) Dimensions shown in millimeters Rev Page BOTTOM VIEW (BALL SIDE UP 2.65 PAD 2. 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SSM2518 ...
Page 48
... SSM2518CBZ-R7 −40°C to +85°C SSM2518CPZ −40°C to +85°C SSM2518CPZ-R7 −40°C to +85°C SSM2518CPZ-RL −40°C to +85°C EVAL-SSM2518Z RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...