tp11368 National Semiconductor Corporation, tp11368 Datasheet

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tp11368

Manufacturer Part Number
tp11368
Description
Octal Adaptive Differential Pcm Processor
Manufacturer
National Semiconductor Corporation
Datasheet

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© 1997 National Semiconductor Corporation
TP11368
Octal Adaptive Differential PCM Processor
General Description
The TP11368 is an octal (8) channel Adaptive Differential
Pulse Code Modulation (ADPCM) transcoder, fully compat-
ible to ITU G.726 recommendation in 40 kbps, 32 kbps,
24 kbps, 16 kbps and ANSI 32 kbps modes. The TP11368
ADPCM processor can operate on up to 16 independent
channels in an 8 kHz frame. Each channel is individually
configured, supporting both full and half duplex operation. All
input/output transfers occur on an interrupt basis using se-
rial, double buffered data registers. Together with National’s
TP3054/57 COMBO
TP11368 forms complete ADPCM channels with Codec/
filtering.
Block Diagram
TRI-STATE
®
and COMBO
®
are registered trademarks of National Semiconductor Corporation.
®
or TP3070/71 COMBO II devices, the
DS012902
FIGURE 1. Block Diagram
Features
n CCITT G.726 compatible at 40, 32, 24, 16 kbps
n ANSI T1.301 compatible at 32 kbps
n 16-channel half-duplex (encode or decode) or 8-channel
n Each channel individually configurable
n Selectable µ-law or A-law PCM coding
n Asynchronous 16 MHz master clock operation
n TTL and CMOS compatible inputs and outputs
n 28-pin PLCC or 24-pin DIP packages
n Power consumption of typ. 6 mW at +5V per full-duplex
n On-Chip Power-On-Reset
n −40˚C to +85˚C operating temperature range
n Single 5V supply
full-duplex operation in 8 kHz frame
channel
www.national.com
March 1997
DS012902-1

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tp11368 Summary of contents

Page 1

... The TP11368 is an octal (8) channel Adaptive Differential Pulse Code Modulation (ADPCM) transcoder, fully compat- ible to ITU G.726 recommendation in 40 kbps, 32 kbps, 24 kbps, 16 kbps and ANSI 32 kbps modes. The TP11368 ADPCM processor can operate independent channels kHz frame. Each channel is individually configured, supporting both full and half duplex operation ...

Page 2

... ADPCM serial clock input. ASCK is used to shift ADPCM data into RSI or out of TSO while CE is active (high). The transfer depends on the logic state of TRB. www.national.com Plastic Dual-In-Line DS012902-2 Order Number TP11368N See NS Package Number N24A CLK Master clock input. CLK may be asynchronous to PSCK or ASCK. CE Chip enable input ...

Page 3

... ADPCM data, which will be shifted out during the third cycle the TSO output with the rising edges of ASCK. The TP11368 requires one master clock signal CLK. The master clock signal CLK is not required to be synchronous to the serial I/O clocks ASCK or PSCK. The serial interface uses the serial clocks ASCK and PSCK and chip enable CE for receiving and transmitting data ...

Page 4

... CE while CE is high. SERIAL I/O Input data is transferred into the TP11368 on the falling edge of the clock signal, while output data is transmitted on the ris- ing edge of the clock signal. PCM data is transferred syn- chronously using PSCK, while ADPCM data is transferred synchronously using ASCK ...

Page 5

... For the encoding opera- tion, the PCM data is stored in the 8-bit shift register at the falling edge of CE while TRB is high. The TP11368 pro- cesses the data within 123 CLK periods during the following cycle of CE. The encoded ADPCM data is loaded into the 5-bit parallel-to-serial output register with the falling edge of CE ...

Page 6

Functional Description www.national.com (Continued) 6 ...

Page 7

Functional Description (Continued) Table 3 shows the position of the ADPCM data in the 5-bit in- put register when five ASCK low going pulses are available while CE is high. Only the last four bits of the ADPCM input register ...

Page 8

... Note unknown (but defined) state SINGLE-CHANNEL INITIALIZATION AND ALL-CHANNEL RESET The TP11368 ADPCM processor can be initialized on a per-channel basis via the use of INIT all-channel ba- sis via the use of RSTB. In both cases, the internal ADPCM variables are initialized to the default values as suggested by the ITU G ...

Page 9

Functional Description (Continued) CHANNEL NOP Each channel can be independently disabled. When logic low on the falling edge of CE, the ADPCM transcoder processing for that channel is disabled. The processor re- quires 4 CLK cycles for ...

Page 10

Absolute Maximum Ratings TGT: FNXref NS0466*) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications GND CC Voltage at Any Digital Inputs or Outputs GND − 0. ...

Page 11

Timing Specifications (Continued) Unless otherwise noted, limits printed in bold characters are guaranteed for V −40˚C to +85˚C by correlation with 100% electrical testing at T production tests and/or product design and characterization. Typical values are specified at V Symbol ...

Page 12

Timing Specifications (Continued) www.national.com 12 ...

Page 13

Applications Information FIGURE 7. Typical Application of ADPCM Transcoders Trunk 13 DS012902-9 www.national.com ...

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... Applications Information FIGURE 8. Timing Diagram of 4 TP11368 (Encoding Trunk Pair Gain System www.national.com (Continued) 14 DS012902-10 ...

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Applications Information (Continued) FIGURE 9. Timing Diagram of ADPCM Decoding Processor 15 DS012902-11 www.national.com ...

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16 ...

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... Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead (0.600" Wide) Molded Dual-In-Line Package Order Number TP11368N NS Package Number N24A 17 www.national.com ...

Page 18

... Italiano National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Order Number TP11368V NS Package Number V28A 2. A critical component in any component of a life support ...

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