lm49350rl National Semiconductor Corporation, lm49350rl Datasheet - Page 33

• Manufacturer Part Number: lm49350rl
• Description: High Performance Audio Codec Sub-system With A Ground-referenced Stereo Headphone Amplifier & An Ultra Low Emi Class D Loudspeaker Amplifier With Dual I2s/pcm Digital Audio Interfaces
• Manufacturer: National Semiconductor Corporation

16.0 PMC Clocks Register
This register is used to control the LM49350's Basic Power Management Setup:
17.0 PMC Clock Divide Register
This register is used to control the LM49350's Power Management Circuits Clocks:
Bits
Bits
1:0
7:0
PMC_CLK_SEL
PMC_CLK_DIV
Field
Field
TABLE 4. PMC_SETUP (0x02h) (Default data value is 0x50h)
This selects the source of the PMC input clock.
This programs the half cycle divider that precedes the PMC. The PMC should run from a
300kHz clock. The default of this divider is 0x50h (divide by 40) to get a
from a 12MHz or 12.288MHz MCLK.
Program this divider with the division you want, multiplied by 2, and subtract 1.
TABLE 3. PMC_SETUP (0x01h)
PMC_CLK_SEL
PMC_CLK_DIV
00000000
00000001
00000010
00000011
00000100
00000101
11111101
11111110
11111111
00
01
10
11
—
33
Description
Description
MCLK (Default divide is 40)
Internal 300kHz Oscillator
PMC Input Clock Source
DAC SOURCE CLOCK
ADC SOURCE CLOCK
Divide by
127.5
126
128
1.5
2.5
—
1
1
2
3
≈
300kHz PMC clock
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