lm49350rl National Semiconductor Corporation, lm49350rl Datasheet - Page 55

• Manufacturer Part Number: lm49350rl
• Description: High Performance Audio Codec Sub-system With A Ground-referenced Stereo Headphone Amplifier & An Ultra Low Emi Class D Loudspeaker Amplifier With Dual I2s/pcm Digital Audio Interfaces
• Manufacturer: National Semiconductor Corporation

The following registers are used to control the LM49350's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is
programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh) registers.
Bits
5:0
Bits
6
0
1
2
3
4
5
6
7
HALF_CYCLE_CLK_
STEREO_SYNC_PHASE
CLOCK_SEL
CLOCK_PHASE
Field
SYNC_INVERT
DIV
RX_ENABLE
TX_ENABLE
CLOCK_MS
SYNC_MS
STEREO
Field
This programs the half-cycle divider that generates the master clocks in the audio port. The input
of this divider should be around 12MHz. The default of this divider is 0x00, i.e. bypassed.
Program this divider with the division you want, multiplied by 2, and subtract 1.
This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider.
0 = DAC_SOURCE_CLK
1 = ADC_SOURCE_CLK
If set, the audio port will receive and transmit stereo data.
If set the input is enabled (enables the SDI port and input shift register and any clock
generation required).
If set the output is enabled (enables the SDO port and output shift register and any clock
generation required).
If set the audio port will transmit the clock when either the RX or TX is enabled.
If set the audio port will transmit the sync signal when either the RX or TX is enabled.
This sets how data is clocked by the Audio Port.
If set, this reverses the left and right channel data of the Audio Port.
If this bit is set the SYNC is inverted before the receiver and transmitter.
TABLE 38. BASIC_SETUP (0x50h/0x60h)
TABLE 39. CLK_GEN_1 (0x51h/0x61h)
STEREO_SYNC_PHASE
HALF_CYCLE_CLK_DIV
CLOCK_PHASE
SYNC_INVERT
000000
000001
000010
000011
111101
111110
11111
0
1
0
1
0
1
—
55
Description
Right channel data goes to right channel output.
Right channel data goes to left channel output.
Left channel data goes to right channel output.
Left channel data goes to left channel output.
PCM (TX on rising edge, RX on falling edge)
Description
I
2
S (TX on falling edge, RX on rising edge)
SYNC Low = Left, SYNC High = Right
SYNC Low = Right, SYNC High = Left
Audio Port Data Orientation
SYNC ORIENTATION
Audio Data Mode
Divides By
BYPASS
31.5
1.5
31
32
—
1
2
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