adl5202 Analog Devices, Inc., adl5202 Datasheet
adl5202
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adl5202 Summary of contents
Page 1
... UP/DOWN INTERFACE Figure 1. the appropriate logic level to the PWUP pin. The quiescent current of the ADL5202 is typically 160 mA. It may be configured for higher quiescent current of 220 mA, in high performance power mode, for more demanding applications. When powered down, the ADL5202 consumes less than 18 mA and offers excellent input to output isolation ...
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... ADL5202 TABLE OF CONTENTS Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Preliminary Technical Data Digital Interface Overview ...............................................................9 Typical Performance Characteristics ........................................... 10 Evaluation Board ............................................................................ 11 Evaluation Board Control Software ......................................... 11 ...
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... Gain Code = 000000 Low p-p OUT p-p OUT Gain Code = 000000 High p-p OUT p-p OUT Gain Code = 000000 Low p-p OUT p-p OUT Rev. PrE | Page ADL5202 Min Typ Max Unit 700 MHz TBD V/nsec 8 V p-p 150 Ω 1.5 V TBD −11.5 dB 0.5 ...
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... ADL5202 Parameter 70 MHz [Nominal Power Mode] Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point NOISE/HARMONIC PERFORMANCE 140 MHz [High Performance Power Mode] Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 140 MHz [Nominal Power Mode] ...
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... Pin PWUP Minimum voltage to enable the device Digital pins Minimum voltage for a logic high Maximum voltage for a logic low PM = Low (High Performance Power Mode High (Nominal Power Mode) PWUP Low Rev. PrE | Page ADL5202 Min Typ Max Unit 7.3 dB −70 dBc − ...
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... ADL5202 ABSOLUTE MAXIMUM RATINGS Table Summary Table 2. Parameter Supply Voltage, V POS PWUP, Digital Pins Input Voltage IN+ IN- Internal Power Dissipation θ (Exposed paddle soldered down) JA θ (Exposed paddle not soldered down) JA θ (At exposed paddle soldered down) JC Maximum Junction Temperature Operating Temperature Range ...
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... INDICATOR ADL5202 MODE1 4 MODE0 5 TOP VIEW PM 6 (Not to Scale) GND 7 SIDO/B5 8 SCLK/B4 9 EXPOSED PADDLE 10 GS1/CSB/ CONNECT Figure 2. 40 Lead LFCSP Rev. PrE | Page ADL5202 VOUTA– VOUTA+ 28 VPOS 27 VPOS 26 VPOS 25 VPOS 24 VPOS 23 VPOS 22 VOUTB+ 21 VOUTB– ...
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... ADL5202 Pin No. Mnemonic Description 17 PWUPB Channel B power up. A logic high on this pin enables the part. 19, 21 VOUTB+ Channel B positive output. 20, 22 VOUTB− Channel B negative output. 23, 24, 25, VPOS Positive power supply. 26, 27, 28, 29, 31 VOUTA+ Channel A positive output 30, 32 VOUTA− Channel A negative output ...
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... Preliminary Technical Data DIGITAL INTERFACE OVERVIEW The ADL5202 DVGA has three digital control interface options: • Parallel Control Interface • Serial Peripheral Interface • Gain Step Up/Down Interface The digital control interface selection is made via 2 digital pins, MODE1 and MODE0, as shown in Table 5. There are two common digital control pins, PM and PWUP ...
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... ADL5202 TYPICAL PERFORMANCE CHARACTERISTICS +20dB 0dB – 11.5dB OUT PER TONE (dBm) Figure 5. OIP3 vs. Power @ 5 Gains 100 150 200 250 300 FREQUENCY (MHz) Figure 6. P1dB Vs. Frequency at Max Gain ...
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... EVALUATION BOARD CONTROL SOFTWARE The ADL5202 evaluation board is configured with a USB- friendly interface to program the gain of the ADL5202. The software GUI (see Figure 11) allows users to select a particular frequency to write to the device and also to read back data from the SDO pin that shows the currently programmed filter setting ...
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... ADL5202 VPOS R67 VXA C36 L1 L3 0.1UF 1UH 1UH NEG VOUTA1N 150 OHM DIFF PAIR POS VOUTA1P VPOS R68 VXB C37 L2 L4 C39 0.1UF 0.1UF 1UH 1UH NEG VOUTB1N 150 OHM DIFF PAIR POS VOUTB1P C38 0.1UF R73 DNI C40 R69 ...
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... Figure 14. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ × Body, Very Thin Quad (CP-40-10) Dimensions shown in millimeters Package Description 40 Lead LFCSP_WQ, 7” Reel 40 Lead LFCSP_WQ, Waffle Pack Evaluation Board Rev. PrE | Page 4.45 EXPOSED PAD 4. 0.25 MIN BOT TOM VIEW Package Option CP-40-10 CP-40-10 ADL5202 ...