adl5202 Analog Devices, Inc., adl5202 Datasheet - Page 11

• Manufacturer Part Number: adl5202
• Description: 31.5 Db Range, 0.5 Db Step Size Programmable Vga
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
EVALUATION BOARD
The ADL5202 evaluation board is available with software
control to program the variable gain control. It is a 4-layer
board with split ground plane for analog and digital sections.
Special care is taken to place the power decoupling capacitors
close to the device pins. The board is designed for easy single-
ended (through a Mini-Circuits TC3-1T+ RF transformer) or
differential configuration for each channel.
EVALUATION BOARD CONTROL SOFTWARE
The ADL5202 evaluation board is configured with a USB-
friendly interface to program the gain of the ADL5202. The
software GUI (see Figure 11) allows users to select a particular
frequency to write to the device and also
to read back data from the SDO pin that shows the currently
programmed filter setting. The software setup files can be down-
loaded from the ADL5202 product page at www.analog.com.
SCHEMATICS AND ARTWORK
INA+
INA-
INB+
INB-
50 OHM SE
50 OHM SE
50 OHM SE
LATCHA
LATCHB
50 OHM SE
MODE0
MODE1
R88
R89
PM
DNI
DNI
0
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
INBP2
R8
0
R9
0
AGND
AGND
6
4
6
4
TC3-1T+
TC3-1T+
3V3
3V3
3V3
3V3
3V3
T1
T2
R10
1K
R11
1K
R12
1K
R13
1K
R14
1K
AGND
AGND
AGND
AGND
AGND
0.1UF
0.1UF
1
2
3
1
2
3
C18
C19
PA0
PB6
PA7
PA6
PA5
R15
1K
R16
1K
R17
1K
R18
1K
R19
1K
NOTE: 150 OHM DIFF PAIRS MADE UP OF 75 OHM SE TRACES.
150 OHM DIFF PAIR
150 OHM DIFF PAIR
AGND
AGND
AGND
AGND
R20
DNI
R21
DNI
R22
DNI
R23
DNI
R24
R25
DNI
DNI
0 Ω
0 Ω
R26
R27
0 Ω
R28
0 Ω
R29
0.1UF
0.1UF
0.1UF
0.1UF
C20
C21
C22
C23
PWUPA
P1
LATCHA
LATCHB
MODE0
MODE1
PWUPB
VINAN
VINAP
VINBN
VINBP
P2
1
2
3
AGND
PM
1
2
3
36
35
15
16
37
14
AGND
6
5
4
3V3
VINA_NEG
VINA_POS
VINB_NEG
VINB_POS
LATCHA
LATCHB
PM
MODE0
MODE1
R30
DNI
AGND
3V3
Figure 12. Evaluation Board Schematic
PWUPB
VPOS
GND
VPOS
Rev. PrE | Page 11 of 13
VPOS
1
UPDN_DAT_A_A0
UPDN_CLK_A_A1
UPDN_DAT_B_B0
UPDN_CLK_B_B1
AGND
GS1_CSB_N_B3
GS0_FA_B_B2
RED
VOUTA_NEG
VOUTA_POS
VOUTA_POS
VOUTA_NEG
VOUTB_POS
VOUTB_NEG
VOUTB_NEG
VOUTB_POS
0.1UF
0.1UF
0.1UF
0.1UF
CSA_N_A3
C24
C25
C26
C27
FA_A_A2
SCLK_B4
SDIO_B5
A4
A5
GND
1
DUT1
ADL5202_PRELIM_V2
30
29
32
31
19
20
21
22
38
39
40
1
2
3
13
12
11
10
9
8
GRN
AGND
VOUTA2N
VOUTA2P
VOUTB2N
VOUTB2P
A0
A1
A2
A3
A4
A5
B0
B1
B2
B3
B4
B5
3V3
1
R64
R63
RED
AGND
C51
0.1UF
0
0
R66
R65
3V3
0
0
VOUTA1N
VOUTA1P
VOUTB1N
VOUTB1P
A4
A0
A1
A2
A3
A5
B0
B1
B2
B3
B4
B5
AGND
AGND
AGND
AGND
Figure 11. Evaluation Control Software
DNI
R31
R32
DNI
R33
R34
DNI
DNI
R35
R36
R37
R38
1K
1K
1K
1K
DNI
C28
DNI
C29
DNI
C30
DNI
C31
PA1
PA4
PB5
PB2
R39
R40
R41
R42
1K
1K
1K
1K
3V3
3V3
3V3
3V3
1
2
3
1
2
3
1
2
3
1
2
3
A0
A3
B0
B3
AGND
AGND
AGND
AGND
DNI
DNI
R45
R84
R46
R85
DNI
DNI
R49
R43
R50
R44
1K
DNI
1K
1K
1K
C32
C47
DNI
C33
DNI
C48
DNI
PA2
PD6
PB4
PB1
R51
R47
R52
R48
1K
1K
1K
1K
3V3
3V3
3V3
3V3
1
2
3
1
2
3
1
2
3
1
2
3
A4
A1
B1
B4
AGND
AGND
AGND
AGND
R86
R53
DNI
R87
R54
DNI
DNI
DNI
ADL5202
R55
R56
R57
R58
1K
DNI
1K
DNI
1K
1K
DNI
C49
C34
C50
DNI
C35
PA3
PD7
PB3
PB0
R59
R60
R61
R62
1K
1K
1K
1K
3V3
3V3
3V3
3V3
1
2
3
1
2
3
1
2
3
1
2
3
A2
A5
B2
B5