clc1001 Cadeka Microcircuits LLC., clc1001 Datasheet - Page 15

• Manufacturer Part Number: clc1001
• Description: Ultra-low Noise Amplifer
• Manufacturer: Cadeka Microcircuits LLC.

Data Sheet
Driving Capacitive Loads
Increased phase delay at the output due to capacitive
loading can cause ringing, peaking in the frequency
response, and possible unstable behavior. Use a series
resistance, R
improve stability and settling performance. Refer to Figure
5.
Table 1 provides the recommended R
capacitive loads. The recommended R
<=1dB peaking in the frequency response. The Frequency
Response vs. C
of the CLC1001.
For a given load capacitance, adjust R
tradeoff between settling time and bandwidth. In general,
reducing R
additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLC1001 will typically recover in less
than 25ns from an overdrive condition. Figure 6 shows the
CLC1001 in an overdriven condition.
©2007-2008 CADEKA Microcircuits LLC
Input
Figure 5. Addition of R
C
L
100
470
10
22
47
(pF)
R
g
S
+
-
Table 1: Recommended R
S
will increase bandwidth at the expense of
, between the amplifier and the load to help
L
R
plots, on page 7, illustrates the response
f
R
4.3
S
43
33
20
13
(Ω)
R
S
s
for Driving Capacitive Loads
C
L
-3dB BW (MHz)
R
L
S
266
228
192
155
84
S
vs. C
Output
S
values result in
to optimize the
S
L
for various
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
▪
▪
▪
▪
▪
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
CEB002
CEB003
Evaluation Board
Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Minimize all trace lengths to reduce series inductances
-1
-2
-3
3
2
1
0
0
50
100
Figure 6. Overdrive Recovery
Input
150
#
CLC1001 in SOT23-5
CLC1001 in SOIC-8
200
Time (us)
Output
250
Products
300
350
www.cadeka.com
G = 10
400
450
6
4
2
0
-2
-4
-6
15