x98021 Intersil Corporation, x98021 Datasheet
x98021
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x98021 Summary of contents
Page 1
... Automatic Black Level Compensation (ABLC™) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. The X98021's digital PLL generates a pixel clock from the analog source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock output frequencies range from 10MHz to 210MHz with sampling clock jitter of 250ps peak to peak ...
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... PART NUMBER X98021L128-3.3 X98021L-3.3 X98021L128-3.3-Z (See Note) X98021L-3.3Z NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Input capacitance INPUT CHARACTERISTICS (HSYNC 1, HSYNC Input Threshold Voltage IH IL Hysteresis R Input impedance IN 3 X98021 Recommended Operating Conditions Temperature (Commercial 0°C to +70°C Supply Voltage 3.3V, pixel rate = 210MHz COMMENT Guaranteed monotonic Per Channel Percent of full scale ADC LSBs (see ABLC™ ...
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... Thermal Resistance, Junction to Ambient JA AC TIMING CHARACTERISTICS PLL Jitter Sampling Phase Steps Sampling Phase Tempco Sampling Phase Differential Nonlinearity HSYNC Frequency Range f Crystal Frequency Range XTAL 4 X98021 = 3.3V, pixel rate = 210MHz COMMENT , RESET) IN RESET has a 70kΩ pullup VSYNC ...
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... NOTES: 1. Setup and hold times are at a 140MHz DATACLK rate SCL t SU:ST t HD:STA SDA IN SDA OUT 5 X98021 = 3.3V, pixel rate = 210MHz COMMENT (Note 1) 15pF DATACLK load, 15pF DATA load (Note 1) 2 XTAL periods min 5 XTAL periods plus SDA’s RC time ...
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... B [7: OUT FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS) 6 X98021 t HOLD t SETUP FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals ...
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... P Video In 0 DATACLK [7: [7: OUT FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING 7 X98021 = 7.5ns + (PHASE/64 +10.5)*t PIXEL Programmable Width and Polarity FIGURE 5. 48 BIT OUTPUT MODE t = 7.5ns + (PHASE/64 +8.5)*t HSYNCin-to-HSout PIXEL ...
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... ADC X98021 X98021 (128-PIN MQFP) TOP VIEW 102 101 100 ...
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... GND RESET 46 Digital input, 5V tolerant, active low, 70kΩ pull- reset the X98021. This pin is not necessary for normal use and may be tied directly to the V XTAL 39 Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for IN recommended loading) ...
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... Internal power for core logic. Connect to VREG CORE Reserved. Do not connect anything to these pins. 10 X98021 DESCRIPTION . This signal is usually not needed - use VSYNC OUT should be used to detect the beginning of a line. This output will pass composite sync signals OUT ...
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... ADDRESS REGISTER (DEFAULT VALUE) 0x01 SYNC Status (read only) 0x02 SYNC Polarity (read only) 0x03 HSYNC Slicer (0x44) 0x04 SOG Slicer (0x08) 11 X98021 BIT(s) FUNCTION NAME 0 HSYNC1 Active 0: HSYNC1 is Inactive 1: HSYNC1 is Active 1 HSYNC2 Active 0: HSYNC2 is Inactive 1: HSYNC2 is Active 2 VSYNC1 Active 0: VSYNC1 is Inactive ...
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... Blue Gain (0x55) 0x09 Red Offset (0x80) 0x0A Green Offset (0x80) 0x0B Blue Offset (0x80) 0x0C Offset DAC Configuration (0x00) 12 X98021 BIT(s) FUNCTION NAME 0 Channel Select 0: VGA1 1: VGA2 1 Input Coupling 0: AC coupled (positive input connected to clamp DAC during clamp time, negative input disconnected from outside ...
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... DC restore (if enabled) - start the ABLC™ function (if enabled), and - update the data to the Offset DACs (always). When in the default internal CLAMP mode, the X98021 automatically generates the CLAMP pulse. If External CLAMP is selected, the Offset DAC values will only change on the leading edge of CLAMP ...
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... ADDRESS REGISTER (DEFAULT VALUE) 0x17 ABLC™ Configuration (0x40) 0x18 Output Format (0x00) 0x19 HSOUT Width (0x10) 0x1A Output Signal Disable (0x00) 14 X98021 BIT(s) FUNCTION NAME 0 ABLC™ disable 0: ABLC™ enabled (default) 1: ABLC™ disabled 1 Reserved Set to 0. 3:2 ABLC™ pixel width Number of black pixels averaged every line for ABLC™ ...
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... In many cases it never settles at all. So precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet. The X98021's DPLL has less than 250ps of jitter, peak to peak, and independent of the pixel rate. The DPLL 15 X98021 ...
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... HSYNC and VSYNC are separate signals. Component YUV Inputs In addition to RGB and RGB with SOG, the X98021 has an option that is compatible with the component YPbPr and YCbCr video inputs typically generated by DVD players. While the X98021 digitizes signals in these color spaces, it does not perform color space conversion ...
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... To minimize the loading on the green channel, the SOG input for each of the green channels should be AC-coupled to the X98021 through a series combination of a 10nF capacitor and a 500Ω resistor. Inside the X98021, a window comparator compares the SOG signal with an internal 4 bit programmable threshold level reference ranging from 0mV to 300mV below the minimum sync level ...
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... XTAL OUT ÷2 SYNC Processing The X98021 can process sync signals from 3 different sources: discrete HSYNC and VSYNC, composite sync on the HSYNC input, or composite sync from a Sync-On-Green (SOG) signal embedded on the Green video input. The X98021 has SYNC activity detect functions to help the firmware determine which sync source is available ...
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... ADC LSB for most input signals. Increasing the ABLC pixel width or the 65MHz ABLC bandwidth settings decreases the ABLC’s absolute 60MHz DC error further. 55MHz ADC 50MHz The X98021 features 3 fully differential, 210MSPS 8 bit ADCs. FN8219.3 March 8, 2006 ...
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... Sampling Phase The X98021 provides 64 low-jitter phase choices per pixel period, allowing the firmware to precisely select the optimum sampling point. The sampling phase register is 0x10. HSYNC Slicer ...
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... Present detects the presence of a low frequency, repetitive signal inside HSYNC, which indicates a VSYNC signal. The CSYNC Present bit should be used to confirm that the signal being received is a reliable composite sync source. SYNC Output Signals The X98021 has 2 pairs of HSYNC and VSYNC output signals, HSYNC VS OUT and IN ...
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... CLKINV pin that will coast the X98021’s PLL during the VSYNC and Macrovision period. Standby Mode The X98021 can be placed into a low power standby mode by writing a 0x0F to register 0x1B, powering down the triple ADCs, the DPLL, and most of the internal clocks. ...
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... EMI Considerations There are two possible sources of EMI on the X98021: • Crystal oscillator. The EMI from the crystal oscillator is negligible. This is due to an amplitude-regulated, low voltage sine wave oscillator circuit, instead of the typical high-gain square wave inverter-type oscillator, so there are no harmonics ...
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... SEC HS (B) OUT Initialization . The X98021 initializes with default register settings for an AC-coupled, RGB input on the VGA1 channel, with a 24 bit output. The following registers should be written to fully enable the chip: • Register 0x1C should be set to 0x49 to improve DPLL performance in video modes • ...
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... The X98021 has a 7 bit address on the serial bus. The upper 6 bits are permanently set to 100110, with the lower bit determined by the state of pin 48. This allows 2 X98021s to be independently controlled while sharing the same bus ...
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... FIGURE 12. VALID START AND STOP CONDITIONS SCL from Host 1 Data Output from Transmitter Data Output from Receiver Start FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER SCL SDA Data Stable FIGURE 14. VALID DATA CHANGES ON THE SDA BUS 26 X98021 Stop 8 Acknowledge Data Change Data Stable 9 FN8219.3 March 8, 2006 ...
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... FIGURE 15. CONFIGURATION REGISTER WRITE 27 X98021 Signals the beginning of serial I/O R/W X98021 Serial Bus Address Write This is the 7 bit address of the X98021 on the 2 wire bus. The A address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. Shift this 0 0 (pin 48) value to left when adding the R/W bit ...
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... This sets the initial address of the X98021’s configuration register for subsequent reading Ends the previous transaction and starts a new one R/W X98021 Serial Bus Address Write This is the 7 bit address of the X98021 on the 2 wire bus. The A address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R (pin 48) indicating next transaction(s) will be a read ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 29 X98021 SEATING PLANE DIMENSION LIST ( FOOTPRINT: 3.200) ...