ml6460 Micro Electronics Corporation, ml6460 Datasheet
ml6460
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ml6460 Summary of contents
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... DVD players, and other YCrCb to Y/C equipment. The ML6460 accepts 8-bit YCrCb video in either CCIR656 or Square Pixel format and generates analog Y, C and CV waveforms complete with Macrovision® copy protection technology and Closed Caption encoding. ...
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... ML6460 PIN CONFIGURATION 2 ML6460 28-Pin SOIC (S28) AV CC1 OUT AGND1 OUT PRESET0 OUT PRESET1 CC2 FIELD 5 24 AGND2 PHERR 6 23 SDATA DV CC1 7 22 SCLK DGND1 8 21 YCRCB0 VSYNC 9 20 YCRCB1 HSYNC 10 19 YCRCB2 YCRCB7 11 18 YCRCB3 YCRCB6 ...
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... YCRCB0 YCRCB digital input bit 0 22 SCLK Serial control bus clock input 23 SDATA Serial control bus data input 24 AGND2 Analog ground pin 25 AV Analog 5V supply pin CC2 26 CV Composite video output OUT 27 Y Luma output OUT 28 C Chroma output OUT ML6460 3 ...
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... ML6460 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied .................................................... –0 Analog and Digital Inputs/Outputs .. –0 Input current per pin ................................... –25 to 25mA ...
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... Note 3: Normalized to burst. (Continued) CONDITIONS SMPTE Color Bars SMPTE Color Bars CONDITIONS 100kHz CLK Max Length for Zero Response Fast mode Slow mode ML6460 MIN TYP MAX UNITS –1 1 IRE 1 º 1 º MIN TYP MAX UNITS 0 0.8 V – 0.8 ...
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... INTRODUCTION The ML6460 is a single-chip NTSC video encoder for generating analog composite (CV) and S-video (Y/C) outputs from YCrCb digital inputs. The ML6460 is a mixed signal processor optimizing SNR and distortion by performing subcarrier generation, sync generation, modulation and upsampling in the digital domain, while performing mixing, reconstruction and gain scaling in the analog domain ...
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... SENSE_HSYNC bit is set (B15=1), the ML6460 will output a logic 0 at the HSYNC pin during the pixels which are blanked. Conversely, when the SENSE_HSYNC bit is cleared (B15=0), the ML6460 will output a logic 1 at the HSYNC pin during the pixels which are blanked. Consequently, the YCRCB<7:0> inputs will be ignored and a constant blanking level will be output to the analog channels YOUT, COUT, and CVOUT ...
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... ML6460 FUNCTIONAL DESCRIPTION fields output to monitor odd/even fields or analog fields (1-2) and (3-4). The ML6460 also supports a frame based synchronization mode (B17 = FSYNC = 1) where a Line 3 HSYNC Coincident Active Edges VSYNC Beginning of an Odd Field Line 265 HSYNC VSYNC Figure 1. Example of the Beginning of the Odd And Even Fields vs. HSYNC and VSYNC in Master Mode. ...
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... EQUALIZING PULSES BURST PHASE 264 265 266 267 268 269 270 START OF VSYNC BURST PHASE 264 265 266 267 268 269 270 ML6460 PULSES 271 272 285 286 271 272 285 286 9 ...
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... ML6460 FUNCTIONAL DESCRIPTION PIXEL SYNCHRONIZATION Master Mode In this mode, the active edge of horizontal sync pulse through the HSYNC pin (configured as an output) indicates the beginning of an active video line (or the beginning of the horizontal blanking) and the multiplexed YCrCb pixel data must be synchronized to ...
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... Figure 4a. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Active Video. (CBLANK = 1, SENSE_HSYNC = 1) (BL = Blanked Pixel) (0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0) (0,0) (0,1) (1,0) BL CB0 Y0 CR0 Selectable Delay Synchronization (0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0) (0,0) (0,1) (1,0) BL CB0 Y0 Y1 CR0 Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0) ML6460 (1, CB2 CR2 (1,1) Y2 CB2 CR2 Y3 11 ...
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... ML6460 CLK (0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0) (0,0) (0,1) HSYNC (output Beginning of Horizontal Blanking Q Clock Cycles # of Clock Cycles SELCCIR = 1 if ANALOG_HBLANK = 0 244 if ANALOG_HBLANK = 1 252 Figure 5. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Horizontal Blanking. (CBLANK = 0, SENSE_HSYNC = 0) (BL = Blanked Pixel) ...
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... CHROMA AND LUMA PROCESSING Refer to Figures 9 through 12. VIDEO OUTPUT STAGE Reconstruction filtering, clamping, and line drivers The ML6460 can simultaneously provide outputs for S- video, two composite video, and a TV modulator. Differential gain and phase are guaranteed at the outputs of the line drivers. Two internal 7 filters and a group delay equalizer are used as reconstruction filters on S-video (NTSC) ...
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... Y634 CR317 Y635 CB318 Y636 CR318 Y637 CB319 Y638 CR319 Y639 1280 in the active portion of a line. EAV and SAV Code Format (8-bits PROTECTION BITS SYNCHRONIZATION (IGNORED BY ML6460) BITS Format <1,F,V,H,P3,P2,P1,P0> Line Number Code EAV ...
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... CR0 CB2 CR2 Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0) Value (SEL_HSYNC1, SEL_HSYNC0) (0,0) A CB0 Bit CR0 CB2 CR2 H Y3 ML6460 (0,1) (1,0) (1, CB0 CB0 BL CR0 Y0 CB0 Y1 CR0 Y0 CB2 Y1 CR0 Y2 CB2 Y1 CR2 Y2 CB2 ...
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... ML6460 CLK HSYNC (input Beginning of Horizontal Blanking P Clock Cycles # of Clock Cycles SELCCIR = 1 If ANALOG_HBLANK = 0 244 If ANALOG_HBLANK = 1 252 Figure 8. Pixel Synchronization. For External Mode, Active Edge at Beginning of Horizontal Blanking. (HRESET_MODE = 0, SENSE_HSYNC = Blanked Pixel) CLK HSYNC (input ...
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... Figure 10. Chroma Bandlimit Filter: Passband (FIR 1 0 –1 –2 –3 –4 –5 – Figure 12. Reconstruction Filter: Passband (Normalized) ML6460 0 0.25 0.5 0.75 1 1.25 1.5 1.75 INPUT FREQUENCY (MHz) Filter) DIGITAL FIR FILTER TOTAL FILTER AND BUFFER RESPONSE ...
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... The polarity of the composite blanking signal is programmable thru the SENSE_HSYNC bit (B15). When the SENSE_HSYNC bit is set (B15=1), the ML6460 will output a logic 0 at the HSYNC pin during the pixels which are blanked. Conversely, when the SENSE_HSYNC bit is cleared (B15=0), the ML6460 will output a logic 1 at the HSYNC pin during the pixels which are blanked. Consequently, the YCRCB< ...
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... HSYNC, VSYNC and FIELD are determined upon selection of this bit. Table 3 provides a summary of Slave / Master modes. When this bit is set (B28=1), the ML6460 is in slave mode. When this bit is cleared (B28=0), the ML6460 is in master mode. Special note for slave modes: this bit (B28) along with the SLAVE_MODE bit (B26) selects between internal (B26=1) and external slave modes (B26=0) ...
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... ANALOG_HBLANK (B23) to choose between "analog" and digital" line encoding. The possible approaches are summarized in Table 4 below.. FULL_BAR, B22 This bit is used to program the ML6460 to encode in normal modes or 100% amplitude video (100% color bar). When this bit is set (B22=1), the ML6460 is ready to handle 100% color bars. With 75% amplitude signals, this bit should be cleared (B22=0) for optimum signal to noise performance ...
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... FIELD pin is configured as an output (see B8). FRAME_MODE, B8 This bit configures the FIELD pin of the ML6460 as an input (if B8= output (if B8=0). YDEL1, B7 This bit, in conjunction with YDEL0 (B6), is used to select luma delay in order to align luma and chroma data ...
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... ML6460 DATA BIT NAME DESCRIPTION B0 AC_DC Configures analog output buffers for drive B1 SUBCARRIER_OFF Disable internal subcarrier oscillator - for test only B2 CC_ALL Enables Closed Caption transmission on every line B3 FIX_SCH Enable reset of subcarrier oscillator every other frame to maintain SCH phase B4 ACTIVE_ON Eliminate H & V intervals, suppress burst — for test only ...
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... ML6460 CC21=1; CC-284=1 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 284 line 284 line 284 line 284 line 284 line 284 ...
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... ML6460 FUNCTIONAL DESCRIPTION PRESET PIN CONTROL The ML6460 can be controlled by a pair of preset mode pins. These pins do not allow access to all of the programmable features of the ML6460, but are intended to provide a simpler interface for most applications. Refer to Table 8 for preset modes. SERIAL BUS OPERATION The serial bus control in the ML6460 has two levels of addressing: Device Addressing and Functional Addressing ...
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... Figure 16. Definition of ADDRESS FORMAT on Serial Data Bus All Other S Transitions Must Occur While S DATA CLK FUNCTION ADDRESS MSB means start of sequence CLK ML6460 t FALL is Low STOP 9th pulse strobes dummy bit for ACK CLK S : ...
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... ML6460 S DATA MSB FROM DEVICE BIT BIT BIT X AND FUNCTION ADDRESS Pulse Strobes Dummy Bit for ACK UPPER BYTE CLOSED CAPTION REGISTER UPPER BYTE MSB A31 A30 A29 A28 A27 A26 UPPER MIDDLE BYTE A23 A22 A21 A20 A19 ...
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... Figure 19. Typical Encoding Application (Low Cost Video Capture or Camera Systems) COPY MPEG-2 PROTECTION VIDEO DECODER MPEG2 VIDEO OUT YCrCb VIDEO PROCESSOR AC-3 AC-3 I/F DECODER RS - 170 VIDEO DECODER Y/C S-VHS YCrCb PCI WAVELET COMPRESSION ML6460 16MB SDRAM VIDEO ANALOG OUT CV ML6460 OR Y ML6461 C AUDIO AUDIO OUT ANALOG OUT CV ML6460 VIDEO OR ANALOG Y ML6461 OUT C 27 ...
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... Figure 21. Typical Encoding Application (MPEG2/Overlay Systems) 28 DAUGHTER CARD YcRcB ML6460 VIDEO ML6461 DECODER RGB ENCODER VMI/VIP PORT YCrCb 3D GRAPHICS PROCESSOR AGP OR PCI CONNECTOR GENLOCK OVERLAY PROCESSOR ALPHAKEY CV SYNC SEPARATOR/ Y/C AGC ML6460 ML6461 Y/C NTSC ENCODER CHROMA LOCK ANALOG FADER Y/C BANDSPLIT CV GENLOCK ...
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... DV CC1 SCLK 21 DGND1 YCRCB0 20 VSYNC YCRCB1 19 HSYNC YCRCB2 18 YCRCB7 YCRCB3 17 YCRCB6 YCRCB4 16 YCRCB5 CLK 15 DV CC2 DGND2 ML6460 C520 S VIDEO R525 220µF 75 C519 R524 220µF 75 RCA J302 CV OUT C518 R523 220µF 75 FB301 V CC FERRITE BEAD C302 C030 0.1µF 47µ ...
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... ORDERING INFORMATION PART NUMBER ML6460CS © Micro Linear 1999 registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; ...