mpc2605 Micro Electronics Corporation, mpc2605 Datasheet
mpc2605
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mpc2605 Summary of contents
Page 1
... PowerPC applications (MPC603 and MPC604). Using 0.38 m technology along with standard cell logic technology, the MPC2605 integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller to provide a 256KB, 512KB Level 2 cache with one, two, or four chips on a 64–bit PowerPC bus. ...
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... DBG U CPU4 CFG0 CFG2 CFG1 DH7 DH5 DH3 DH1 W DP0 DH6 DH4 DH2 DH0 DH15 DH12 MPC2605 2 PIN ASSIGNMENT DH31 DH29 DH27 DH26 DL16 DL19 DL22 DH16 DH30 DH28 DH25 DL17 DL20 DL23 ...
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... CPU BR. I MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor configuration as the third CPU BR. I MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor configuration as the fourth CPU BR. I CPU data bus grant input from arbiter. I MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor configuration as the second CPU DBG ...
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... Data bus high input and output. DH0 is the MSB. DH31 is the LSB. I/O Data bus busy. Used as input when processor is master, driven as an output after a qualified L2 DBG when MPC2605 is the bus master. Note: To operate in Fast L2 mode, this pin must be tied high. I/O Data bus parity input and output. ...
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... Signals the start of either a processor or bus master cycle. I/O Transfer size I/O from processor bus. I/O Transfer type I/O from processor bus. I/O Write through status input from processor bus. When tied to ground, the MPC2605 will operate in write–through mode only (no copy–back). Supply Power supply: 3.3 V 5%. Supply Ground. — ...
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... Thermal Resistance Junction to Ambient (Still Air, Test Board with Two Internal Planes) Thermal Resistance Junction to Ambient (200 lfpm, Test Board with Two Internal Planes) Thermal Resistance Junction to Board (Bottom) Thermal Resistance Junction to Case (Top) MPC2605 6 (Voltages Referenced Symbol V DD ...
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... Timing Timing Reference , CLOCK INPUT TIMING DIAGRAM 1 Termination to 1.5 V MPC2605– Unit Notes N Min Max — 66.67 MHz 15 — ns 1.0 2 — 150 MPC2605 7 ...
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... All input specifications are measured from the TTL level (0 the signal in question to the 1.4 V level of the rising edge of the input clock. Both input and output timings are measured at the pin. 2. This parameter is sampled and not 100% tested. CLK INPUTS OUTPUTS MPC2605 8 Timing Timing Reference MPC2605–66 Min Max U i Unit N Notes 15 — ns 4.5 — — — ...
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... If ARTRY is asserted during a read hit, the MPC2605 will abort the process processor burst write occurs right after a snoop write that was a cache hit, the MPC2605 will invalidate the line. If the snoop was a cache miss, the MPC2605 will not perform a write allocate. ...
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... These are called snoop data tenures. Because these two types of systems are fundamentally dif- ferent, the MPC2605 must know in which type of system it is resident in order to respond properly to the different types of transactions. For systems that do not have snoop data ten- ures, CFG3 must be tied high ...
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... MPC2605 is prepared to take action on the next transaction initiated by the processor. At some point after this 4000 cycle sequence, the MPC2605 will detect its first cache hit. At this time the system will experience its first assertion of L2 CLAIM. If the memory controller must be configured via software to comprehend assertions of L2 CLAIM, this configuration operation must have completed by this time ...
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... Processor Reads When the processor issues a read transaction, the MPC2605 does a tag lookup to determine if this data is in the cache. If there is a cache hit and CI is not asserted, the MPC2605 will assert L2 CLAIM and supply the data to the processor when the data tenure starts. ...
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... The other situation that can cause problems with a shared bus request occurs when a snoop hits a dirty line in one of the MPC2605 devices. If device one has a cache line in its COB, it will assert that it may perform a castout operation snoop hits a dirty line in device two, it will as- sert both ARTRY and that it can write the snoop data back to main memory ...
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... The only way to ensure that no new transactions will occur is for the MPC2605 to be granted the bus. Thus, upon entering the sequence initiated by the assertion of L2 FLUSH, the MPC2605 will assert L2 BR. As soon asserted, the MPC2605 can start stepping through the tag RAM entries ...
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... High–Z MOTOROLA be a qualified assertion of CPU DBG in the same cycle as the assertion of TS for the MPC2605 to respond with TA in the next cycle. CPU DBG does not affect the timing of L2 CLAIM or AACK. The write hit timing is virtually the same. The only dif- ference is the processor drives the data instead of the MPC2605 ...
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... LEGEND Signal driven to the MPC2605 Signal driven by the MPC2605 High–Z Figure 2. Multiple Burst Read (or Write) Hits MPC2605 16 the data tenure for the first TS is done. The MPC2605 asserts AACK at the same time as the fourth TA for data tenures that it controls ...
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... Figure 3. Read Miss Followed by a Burst Read Hit for MPC603/604 MOTOROLA the read miss. This is because the MPC2605 is not in control of TA for the first access and must, therefore, wait until the first access’ data tenure is complete before it can drive AACK true for the read hit ...
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... Signal driven by the MPC2605 High–Z Figure 4. Multiple Burst Read Hits in Fast L2 Mode MPC2605 requirement for data streaming. Note also that DBB is not shown. For proper operation in Fast L2 mode the DBB pin of the MPC2605 must be tied to a pull–up resistor ...
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... Figure 5 shows the fastest possible burst write hit to a write–through mode L2 cache line, read miss or write miss processing that replaces a clean line. For these operations MPC2605 will not assert any signals on the 60X bus. A cache line is considered write through asserted by CLK ...
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... READ/WRITE MISS Figure illustration of a processor read or write miss that causes the MPC2605 to replace a dirty line asserted two clocks after TS. The dirty data to be replaced is moved into the internal cast out buffer (COB) at the same time the new data is written into the cache. Note that the ...
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... MPC2605 will assert ARTRY through the cycle following the assertion of AACK. This cycle is called the ARTRY window. Note that the MPC2605 also asserts the same time it asserts ARTRY. Because the snoop could also have hit a dirty line in the processor’s cache, the MPC2605 samples ...
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... Figure 8. Read or Write Snoop Hit to Dirty L2 Cache Line and Dirty Processor Cache Line MPC2605 22 the MPC2605 will negate L2 BR. It will also ignore assertions of L2 BG. This allows the processor to write back its dirty cache line, at which time the MPC2605 will either update or invalidate its copy depending on whether snoop read or snoop write ...
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... High–Z Figure 9. Burst Read (or Write) Hit Without CPU DBG Parked MOTOROLA the response for a read hit from the MPC2605 is gated by the assertion of CPU DBG. The fastest response possible in a system that does not park CPU DBG is 3–1–1–1. ...
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... CKZ t CKX TMS t s TDI t sd TMS t h TDI CKH CKL CKZ Figure 10. TAP Controller Timing . . . . . . . . . . . . . . . . . . . . . . . 1 Termination to 1.5 V MPC2605–66 Min Max U i Unit Notes N 30 — — — ...
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... TRST should be tied ensure proper HRESET op- eration. Although TDI and TMS are designed in such a way that an undriven input will produce a response equivalent to the application of a logic still advisable to tie these inputs through a 1K resistor. TDO should remain unconnected. MPC2605 25 ...
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... TEST–LOGIC 1 RESET 0 1 RUN–TEST/ 0 IDLE NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK. MPC2605 26 SELECT DR–SCAN CAPTURE–DR 0 SHIFT– EXIT1–DR 0 PAUSE 1– EXIT2–DR 1 UPDATE–DR ...
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... DOE I/O DOE I/O DOE I/O DOE I/O DOE I/O DOE I/O DOE I/O DOE I/O DOE I/O DOE I/O DOE I/O DOE Input Input I/O ABBOE Input Input Input Input Input Input I/O FDNOE Input I/O L2BROE I/O TAOE Output L2CLAIMOE Input I/O AACKOE I/O AOE I/O ARTRYOE I/O AOE Input Input Input I/O DBBOE Input I/O AOE I/O AOE I/O AOE MPC2605 27 ...
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... I/O 99 DL3 I/O 100 DL4 I/O 101 DL5 I/O 102 DL6 I/O 103 DL7 I/O 104 DP4 I/O 105 DL8 I/O 106 DL9 I/O MPC2605 28 Output Bit Enable Number Bit/Pin Name AOE 107 DL10 AOE 108 DL11 AOE 109 DL12 AOE 110 DL13 111 DL14 112 DL15 113 DP5 114 ...
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... AOE 164 AOE AOE 165 APEOE 166 167 168 ORDERING INFORMATION (Order by Full Part Number) MPC 2605 Full Part Number — MPC2605ZP66 MPC2605ZP66R Bit/Pin Output Type Enable FDNOE Output Enable DBBOE Output Enable DOE Output Enable ARTRYOE Output Enable ...
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... NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM C. MILLIMETERS DIM MIN MAX A ––– 2.05 A1 0.50 0.70 A2 0.95 1.35 A3 0.70 0.90 b 0.60 0.90 D 25.00 BSC D1 22.86 BSC D2 22.40 22.60 e 1.27 BSC E 25.00 BSC E1 22.86 BSC E2 22.40 22.60 Mfax is a trademark of Motorola, Inc. MPC2605/D MOTOROLA ...