mpc2605 Micro Electronics Corporation, mpc2605 Datasheet - Page 21

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mpc2605

Manufacturer Part Number
mpc2605
Description
Integrated Secondary Cache Powerpc Microprocessors
Manufacturer
Micro Electronics Corporation
Datasheet

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READ/WRITE SNOOP HIT (DIRTY L2 LINE)
cache line that is dirty in the L2, but is not dirty in the
processor’s cache. When a snoop hits a dirty line, the
MPC2605 will assert ARTRY through the cycle following the
assertion of AACK. This cycle is called the ARTRY window.
Note that the MPC2605 also asserts L2 BR at the same time
it asserts ARTRY. Because the snoop could also have hit a
dirty line in the processor’s cache, the MPC2605 samples
DH0 – DH31,
MOTOROLA
DL0 – DL31
L2 CLAIM
CPU DBG
A0 – A31
Figure 7 is an illustration of a read or write snoop to a
CPU BG
CPU BR
L2 DBG
ARTRY
L2 BG
L2 BR
AACK
DBB
CLK
TS
TA
LEGEND
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
Figure 7. Read or Write Snoop Hit to Dirty L2 Cache Line and Clean Processor Cache Line
1
A
2
3
4
the processor’s BR signal the cycle following the ARTRY
window. This cycle is called the BR window. If the
processor’s BR signal is not asserted, the MPC2605 will start
sampling L2 BG, the cycle after the BR window.
burst. The earliest that it can handle the first assertion of TA
is two cycles after its assertion of TS.
5
Note that the MPC2605 cannot do a 2–1–1–1 copy back
6
7
A
8
A1
9
10
A2
A
11
A3
MPC2605
12
A4
21

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