mpc2605 Micro Electronics Corporation, mpc2605 Datasheet - Page 22

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mpc2605

Manufacturer Part Number
mpc2605
Description
Integrated Secondary Cache Powerpc Microprocessors
Manufacturer
Micro Electronics Corporation
Datasheet

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READ/WRITE SNOOP HIT (DIRTY L2 AND PROCESSOR LINE)
L2 cache line is shown in Figure 8. The processor has a dirty
copy of the cache line. In this case, both the processor and
the MPC2605 assert ARTRY. This situation is detected by
sampling CPU BR in the BR window, as described in the
previous example. If CPU BR is asserted in the BR window,
MPC2605
DH0 – DH31,
22
DL0 – DL31
L2 CLAIM
CPU DBG
An illustration of PowerPC read or write snoop hit to a dirty
A0 – A31
CPU BR
CPU BG
L2 DBG
ARTRY
L2 BG
L2 BR
AACK
DBB
CLK
TS
TA
LEGEND
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
Figure 8. Read or Write Snoop Hit to Dirty L2 Cache Line and Dirty Processor Cache Line
1
A
2
3
4
5
the MPC2605 will negate L2 BR. It will also ignore assertions
of L2 BG. This allows the processor to write back its dirty
cache line, at which time the MPC2605 will either update or
invalidate its copy depending on whether it is a snoop read or
snoop write.
6
7
A
8
A1
9
10
A2
11
A3
A
12
A4
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