mpc2605 Micro Electronics Corporation, mpc2605 Datasheet - Page 3

• Manufacturer Part Number: mpc2605
• Description: Integrated Secondary Cache Powerpc Microprocessors
• Manufacturer: Micro Electronics Corporation

* See pin diagram (page 2) for specific pin assignment of these bus signals.
MOTOROLA
PIN DESCRIPTIONS
19G, 17H – 19H, 17J – 19J,
17M – 19M, 17N – 19N,
17P – 19P, 17R – 19R,
17K – 19K, 17L – 19L,
18T, 19T, 18U, 19U,
17C – 19C, 17D
18V, 19V, 18W
Pin Locations
19B
18E
17E
3M
2M
3G
2A
1G
2U
2V
1V
2B
2G
3E
1B
2H
2D
2C
1U
3D
3C
1T
1F
*
*
CPU2 DBG
CPU3 DBG
AP0 – AP3
Pin Name
CPU DBG
CPU2 BG
CPU3 BG
CPU4 BG
CPU2 BR
CPU3 BR
CPU4 BR
A0 – A31
CPU BG
CPU BR
ARTRY
AACK
APEN
CFG0
CFG1
CFG2
CFG3
CFG4
ABB
APE
CLK
CI
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Address inputs from processor. Can also be outputs for processor snoop
addresses. A0 is the MSB. A31 is the LSB.
Address acknowledge input/output.
Used as an input to qualify bus grants. Driven as an output during address tenure
initiated by the MPC2605.
Address parity.
Address parity error. When an address parity error is detected, APE will be driven
low one clock cycle after the assertion of TS then High–Z following clock cycle.
Address parity enable. When tied low, enables address parity bits and the
address parity error bit.
Address retry status I/O. Generated when a read or write snoop to a dirty
processor cache line has occurred.
Configuration inputs. These must be tied to either V DD or V SS .
CFG0
CFG3
CFG4
Cache inhibit I/O.
Clock input. This must be the same as the processor clock input.
CPU bus grant input.
MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the second CPU BG.
MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the third CPU BG.
MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the fourth CPU BG.
CPU bus request input.
MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the second CPU BR.
MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the third CPU BR.
MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the fourth CPU BR.
CPU data bus grant input from arbiter.
MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the second CPU DBG.
MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the third CPU DBG.
0
0
0
1
1
1
1
CFG1
Snoop Data Tenure Selector
0
1
AACK Driver Enable
0
1
0
1
1
0
0
1
1
Supports snoop data tenure
Does not support snoop data tenure
Disable AACK driver
Enable AACK driver
CFG2
0
0
1
0
1
0
1
Description
256KB
512KB; A26 = 0
512KB; A26 = 1
1MB; A25 – A26 = 00
1MB; A25 – A26 = 01
1MB; A25 – A26 = 10
1MB; A25 – A26 = 11
MPC2605
3