DS1000-35 Dallas Semiconductor, DS1000-35 Datasheet - Page 4

• Manufacturer Part Number: DS1000-35
• Description: 5-tap Silicon Delay Line
• Manufacturer: Dallas Semiconductor

TEST CIRCUIT Figure 3
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
input pulse.
t
input pulse.
t
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1000.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
WI
RISE
FALL
PLH
PHL
(Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
(Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
(Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
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DS1000