24lcs21 Microchip Technology Inc., 24lcs21 Datasheet - Page 11

• Manufacturer Part Number: 24lcs21
• Description: 1k 2.5v Dual Mode I 2 C? Serial Eeprom
• Manufacturer: Microchip Technology Inc.

6.0
When using the 24LCS21 in the Bidirectional mode, the
V
ting V
setting V
array. Connecting the V
24LCS21 to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-Only mode.
Additionally, pin 3 performs a flexible write-protect
function. The 24LCS21 contains a write protection
control fuse whose factory default state is cleared.
Writing any data to address 7Fh (normally the
checksum in DDC applications) sets the fuse which
enables the WP pin. Until this fuse is set, the 24LCS21
is always write enabled (if V
set, the write capability of the 24LCS21 is determined
by WP (Figure 6-1).
TABLE 6-1:
© 2005 Microchip Technology Inc.
CLK
V
pin operates as the write-protect control pin. Set-
CLK
CLK
0
1
1
1
CLK
WRITE PROTECTION
high allows normal write operations, while
low prevents writing to any location in the
1/open
WRITE-PROTECT TRUTH
TABLE
WP
X
X
0
CLK
pin to V
CLK
Add. 7Fh
Written
Yes
Yes
No
= 1). After the fuse is
X
SS
would allow the
Read-only
Read-only
Mode
R/W
R/W
7.0
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
The 24LCS21 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24LCS21
issues an acknowledge and transmits the eight-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LCS21
discontinues transmission (Figure 7-1).
FIGURE 7-1:
7.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LCS21 as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LCS21 will then
issue an acknowledge and transmits the eight-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LCS21
discontinues transmission (Figure 7-2).
Bus Activity
Master
SDA Line
Bus Activity
READ OPERATION
Current Address Read
Random Read
T
S
A
R
T
S
1 0 1 0 0 0 0 1
CURRENT ADDRESS
READ
Control
Byte
24LCS21
A
C
K
DS21127F-page 11
Data n
N
O
A
C
K
S
O
P
P
T