24lcs21 Microchip Technology Inc., 24lcs21 Datasheet - Page 4

• Manufacturer Part Number: 24lcs21
• Description: 1k 2.5v Dual Mode I 2 C? Serial Eeprom
• Manufacturer: Microchip Technology Inc.

24LCS21
2.0
The 24LCS21 operates in two modes, the Transmit-
Only mode and the Bidirectional mode. There is a
separate two-wire protocol to support each mode, each
having a separate clock input but sharing a common
data line (SDA). The device enters the Transmit-Only
mode upon power-up. In this mode, the device
transmits data bits on the SDA pin in response to a
clock signal on the V
this mode until a valid high-to-low transition is placed
on the SCL input. When a valid transition on SCL is
recognized, the device will switch into the Bidirectional
mode. The only way to switch the device back to the
Transmit-Only mode is to remove power from the
device.
2.1
The device will power-up in the Transmit-Only mode at
address 00h. This mode supports a unidirectional two-
wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the
FIGURE 2-1:
FIGURE 2-2:
DS21127F-page 4
V
V
SDA
SCL
V
SDA
CLK
SCL
CLK
FUNCTIONAL DESCRIPTION
Transmit-Only Mode
CC
CLK
TRANSMIT-ONLY MODE
DEVICE INITIALIZATION
T
High-impedance for 9 clock cycles
VAA
pin. The device will remain in
T
VHIGH
T
1
VPU
Bit 1 (LSB)
T
VLOW
2
T
VAA
Null Bit
Transmit-Only mode (see Initialization Procedure,
below). In this mode, data is transmitted on the SDA pin
in 8-bit bytes, with each byte followed by a ninth, null bit
(Figure 2-1). The clock source for the Transmit-Only
mode is provided on the V
put on the rising edge on this pin. The eight bits in each
byte are transmitted Most Significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the internal Address Pointers will wrap around to the
first memory location (00h) and continue. The
Bidirectional mode clock (SCL) pin must be held high
for the device to remain in the Transmit-Only mode.
2.2
After V
mit-Only mode. Nine clock cycles on the V
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit in address 00h.
(Figure 2-2).
8
CC
Initialization Procedure
has stabilized, the device will be in the Trans-
9
Bit 1 (MSB)
T
© 2005 Microchip Technology Inc.
VAA
CLK
10
pin, and a data bit is out-
Bit 8
T
VAA
11
Bit 7
CLK
Bit 7
pin must