at88sc0104c ATMEL Corporation, at88sc0104c Datasheet - Page 38

• Manufacturer Part Number: at88sc0104c
• Description: Cryptomemory Specification For Standard Mode Of Operation
• Manufacturer: ATMEL Corporation

8. Asynchronous T=0 Protocol
8.1
8.2
34
Character format
Command format
AT88SC0104/0204/0404/0808/1616/3216/6416/12816/25616C
CryptoMemory complies with the asynchronous T=0 protocol defined in ISO 7816-3. The char-
acter format is shown in the following figure: note that the byte is transmitted with the least
significant bit first.
Even parity is used: the parity bit is such that the overall sum of bits in the data byte and the par-
ity bit is an even number. If a transmission error is detected, the receiving device indicates this
by applying a low level on the I/O channel during the guard time. This tells the transmitting
device to retransmit the byte.
The command sequence is as follows:
Note: for all bytes transmitted by the device or by the host, including header, procedure, status
and data bytes, if a parity error is detected, the receiver requests that byte to be sent again (see
character format).
1. In compliance with ISO 7816-3, the host must send the header consisting of 5 charac-
2. The device replies with a "procedure byte", normally equal to the INS code received. If
3. Data transfer (P3 bytes).
4. A final SW1-SW2 sequence gives the status of the device after completion of the com-
ters: CLA, INS, P1, P2, P3.
a. CLA refers to a class of instructions. This byte isn't tested by the device.
b. INS is the instruction byte.
c. P1 and P2 are reference bytes, such as a data byte address or password index.
d. P3 is the number of data bytes transferred during the command. For outgoing
a problem occurred, then the device will respond with a status word pair SW1-SW2,
indicating the end of the command.
mand. A normal completion is indicated by SW1-SW2 = $90-$00.
I/O
A
Z
transfers (e.g. read commands), P3 = 0 means that 256 data bytes will be emitted
by the card. For incoming commands, P3 = 0 means that no data bytes will be
transferred.
Start bit
0
t
d
1
0
d
1
(n ± 0,2) etu
d
2
8 data bits
d
3
d
4
d
5
d
6
t
d
n
7
Parity bit
p
t
Guard Time
10
Next Start bit
5210A–SMIC–04/07