is42s16100f-7tla1 Integrated Silicon Solution, Inc., is42s16100f-7tla1 Datasheet - Page 39

• Manufacturer Part Number: is42s16100f-7tla1
• Description: 512k Words X 16 Bits X 2 Banks 16mb Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42/45S16100F, IS42VS16100F
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The SDRAM can input data continuously from the burst
start address (a) to location a+255 during a write cycle
in which the burst length is set to full page. The SDRAM
repeats the operation starting at the 256th cycle with
data input returning to location (a) and continuing with
a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
06/03/2010
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the CAS latency, two clock cycles (t
U/LDQM pins goes HIGH, the corresponding outputs go
to the HIGH impedance state. Subsequently, the outputs
are maintained in the high impedance state as long as
that U/LDQM pin remains HIGH. When the U/LDQM pin
goes LOW, output is resumed at a time t
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
DQ8-DQ15
DQ
DQ0-DQ 7
UDQM
LDQM
READ (CA=A, BANK 0)
CLK
WRITE A0
D
IN
READ (CA=A, BANK 0)
A0
READ A0
qmd
D
DATA MASK (UPPER BYTE)
IN
) after one of the
A1
qmd
later. This
D
IN
DATA MASK (LOWER BYTE)
t
QMD=2
D
A
D
OUT
OUT
A0
A0
D
IN
must be executed within the ACT to PRe command
period (t
After the period (t
stop following the execution of the burst stop command
has elapsed, the write cycle terminates. This period
(t
latency.
output control operates independently on a byte basis
with the UDQM pin controlling upper byte output (pins
DQ8-DQ15) and the LDQM pin controlling lower byte
output (pins DQ0 to DQ7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
A1
D
wbd
OUT
HI-Z
) is zero clock cycles, regardless of the CAS
A1
D
ras
IN
D
A2
OUT
max.) following the burst stop command.
HI-Z
BURST STOP
A2
wbd
BST
INVALID DATA
D
t
) required for burst data input to
WBD=0
OUT
A3
PRECHARGE (BANK 0)
PRE 0
HI-Z
t
RP
Don't Care
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