is42s16100a1 Integrated Silicon Solution, Inc., is42s16100a1 Datasheet

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... Integrated Silicon Solution, Inc. — www.issi.com — Rev. C 08/12/03 DESCRIPTION ISSI ’s 16Mb Synchronous DRAM IS42S16100A1 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. ...

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... IS42S16100A1 PIN FUNCTIONS Pin No. Symbol Type A0-A10 Input Pin A11 Input Pin CAS 16 Input Pin 34 CKE Input Pin 35 CLK Input Pin CS 18 Input Pin DQ0 to DQ Pin 12, 39, 40, 42, 43, DQ15 45, 46, 48, 49 14, 36 LDQM, Input Pin ...

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... IS42S16100A1 FUNCTIONAL BLOCK DIAGRAM CLK CKE COMMAND CS DECODER RAS CAS & CLOCK WE MODE GENERATOR A11 REGISTER 11 A10 SELF A9 REFRESH REFRESH A8 CONTROLLER CONTROLLER A7 A6 REFRESH A5 COUNTER ROW ADDRESS LATCH 11 Integrated Silicon Solution, Inc. — www.issi.com — Rev. C 08/12/03 MEMORY CELL ROW ...

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... IS42S16100A1 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG DC RECOMMENDED OPERATING CONDITIONS ...

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... IS42S16100A1 DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level Output Low Voltage Level Operating Current (1,2) CC1 I Precharge Standby Current CKE CC2P I (In Power-Down Mode) CC2PS I Active Standby Current CC3N I (In Non Power-Down Mode) ...

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... IS42S16100A1 AC CHARACTERISTICS Symbol Parameter Units t 3 Clock Cycle Time Access Time From CLK ( CLK HIGH Level Width CHI t CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time Output HIGH Impedance Time ...

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... IS42S16100A1 OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency CAS Latency t CAC t Active Command To Read/Write Command Delay Time RCD RAS Latency ( RAC RCD CAC t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ...

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... IS42S16100A1 COMMANDS Active Command CLK HIGH CKE CS RAS CAS WE A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 Write Command CLK HIGH CKE CS RAS CAS WE A0-A9 COLUMN AUTO PRECHARGE A10 NO PRECHARGE BANK 1 A11 BANK 0 Notes: 1. A8-A9 = Don’t Care. 8 Read Command CLK HIGH CKE CS RAS CAS ...

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... IS42S16100A1 COMMANDS (cont.) No-Operation Command CLK HIGH CKE CS RAS CAS WE A0-A9 A10 A11 Mode Register Set Command CLK HIGH CKE CS RAS CAS WE A0-A9 OP-CODE A10 OP-CODE A11 OP-CODE Integrated Silicon Solution, Inc. — www.issi.com — Rev. C 08/12/03 Device Deselect Command CLK HIGH CKE CS RAS ...

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... IS42S16100A1 COMMANDS (cont.) Self-Refresh Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 Clock Suspend Command CLK CKE BANK(S) ACTIVE CS NOP NOP RAS NOP CAS NOP WE A0-A9 A10 A11 10 Power Down Command CLK CKE ALL BANKS IDLE CS RAS CAS WE NOP A0-A9 A10 A11 Burst Stop Command ...

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... MCD command execution. Active Command (CS, RAS = LOW, CAS, WE= HIGH) The IS42S16100A1 includes two banks of 4096 rows each. This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs ...

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... IS42S16100A1 Self-Refresh Command (CS, RAS, CAS, CKE = LOW HIGH) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh operation is started by dropping the CKE pin from HIGH to LOW. The self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins ...

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... IS42S16100A1 COMMAND TRUTH TABLE Symbol Command MRS Mode Register Set REF Auto-Refresh (5) SREF Self-Refresh (5,6) PRE Precharge Selected Bank PALL Precharge Both Banks ACT Bank Activate (7) WRIT Write WRITA Write With Auto-Precharge READ Read (8) READA Read With Auto-Precharge BST Burst Stop (9) NOP ...

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... IS42S16100A1 OPERATION COMMAND TABLE Current State Command Idle DESL NOP BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Active DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Read DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Write DESL ...

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... IS42S16100A1 OPERATION COMMAND TABLE Current State Command Write With DESL Auto-Precharge NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Precharge DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Immediately DESL Following NOP Row Active BST READ/READA WRIT/WRITA ACT PRE/PALL ...

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... The IS42S16100A1 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 13. The IS42S16100A1 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. ...

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... IS42S16100A1 CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh Undefined Self-Refresh Recovery Self-Refresh Recovery Illegal (2) Illegal (2) Self-Refresh Self-Refresh Recovery Idle State After t Idle State After t Illegal Illegal Power-Down on the Next Cycle Power-Down on the Next Cycle Illegal Illegal Clock Suspend Termination on the Next Cycle ...

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... IS42S16100A1 TWO BANKS OPERATION COMMAND TRUTH TABLE CS CS RAS RAS CAS CAS CS CS RAS CS RAS CAS RAS CAS CAS WE Operation DESL H X NOP L H BST L H READ/READA L H WRIT/WRITA L H ACT L L PRE/PALL L L REF L L MRS L L Notes HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address 2 ...

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... IS42S16100A1 SIMPLIFIED STATE TRANSITION DIAGRAM WRIT CKE_ CKE CLOCK WRITA SUSPEND CKE_ CKE POWER APPLIED Automatic transition following the completion of command execution. Transition due to command input. Integrated Silicon Solution, Inc. — www.issi.com — Rev. C 08/12/03 (One Bank Operation) SREF entry MODE MRS ...

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... The burst length field in the mode register stipulates the number of data items input or output in sequence. In the IS42S16100A1 product, a burst length full page can be specified. See the table on the next page for details on setting the mode register ...

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... IS42S16100A1 MODE REGISTER WRITE MODE LT MODE M11 M10 Integrated Silicon Solution, Inc. — www.issi.com — Rev. C 08/12/03 Address Bus Mode Register (Mx Burst Length Burst Type Latency Mode 0 M7 Write Mode ...

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... IS42S16100A1 BURST LENGTH AND COLUMN ADDRESS SEQUENCE Column Address Burst Length Full Page n n (256) Notes: 1. The burst length in full page mode is 256. 22 Address Sequence ...

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... IS42S16100A1 BANK SELECT AND PRECHARGE ADDRESS ALLOCATION Row X0 — X1 — X2 — X3 — X4 — X5 — X6 — X7 — X8 — X9 — X10 0 1 X11 0 1 Column Y0 — Y1 — Y2 — Y3 — Y4 — Y5 — Y6 — Y7 — Y8 — Y9 — Y10 0 1 Y11 0 1 Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S16100A1 Burst Read The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the clock signal after the CAS latency period. Next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal ...

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... IS42S16100A1 Read With Auto-Precharge The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge com- pletes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation ...

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... IS42S16100A1 Write With Auto-Precharge The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation ...

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... IS42S16100A1 Interval Between Read Command A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command ...

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... IS42S16100A1 Interval Between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The I/On pins must be placed in the HIGH impedance state at least one cycle before data is output during this operation ...

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... IS42S16100A1 Interval Between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i.e., before that cycle completes. Data corresponding to the new write command can be input at the point new write command is executed. To prevent collision ...

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... IS42S16100A1 Precharge The precharge command sets the bank selected by pin A11 to the precharged state. This command can be executed at a time t following the execution of an active command to RAS the same bank. The selected bank goes to the idle state at a time t following the execution of the precharge command, ...

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... IS42S16100A1 Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (t ) from the precharge command to the point WDL where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS ...

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... The IS42S16100A1 can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IS42S16100A1 repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle ...

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... IS42S16100A1 Write Cycle (Full Page) Interruption Using the Burst Stop Command The IS42S16100A1 can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. The IS42S16100A1 repeats the operation starting at the 256th cycle with data input returning to location (a) and continuing with a+1, a+2, a+3, etc ...

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... CAS latency, as soon as one of the U/LDQM pins goes HIGH, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be muted as long as that U/LDQM pin remains HIGH. The IS42S16100A1 will revert to accepting input as soon as CLK COMMAND UDQM LDQM ...

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... CAS latency = 3 Clock Suspend When the CKE pin is dropped from HIGH to LOW during a read or write cycle, the IS42S16100A1 enters clock suspend mode on the next CLK rising edge. This command reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low ...

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... IS42S16100A1 OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle CLK t CHI HIGH CKE RAS CAS A0- A10 BANK 0 & 1 A11 DQM HIGH DQ WAIT TIME t RP T=100 µs < ...

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... IS42S16100A1 Power-Down Mode Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0- A10 BANK 0 & 1 BANK A11 BANK 1 BANK 0 DQM < > PRE < > PALL CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S16100A1 Auto-Refresh Cycle CLK t CHI CKS CKE RAS CAS A0- A10 BANK 0 & 1 A11 DQM < > PALL CAS latency = < > < > REF REF Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S16100A1 Self-Refresh Cycle CLK t CHI CKS CL CKE t CKA RAS CAS A0- A10 BANK 0 & 1 A11 DQM < > PALL CAS latency = 2, 3 Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS42S16100A1 Read Cycle T0 T1 CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > < ACT READ CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don’ ...

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... IS42S16100A1 Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > < ...

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... IS42S16100A1 Read Cycle / Full Page T0 T1 CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD t RAS t RC (BANK 0) < > ...

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... IS42S16100A1 Read Cycle / Ping-Pong Operation (Bank Switching CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RRD (BANK ...

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... IS42S16100A1 Write Cycle CLK t CHI t t CKS t CK CKE t CKA RAS CAS ROW A0- ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don’ ...

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... IS42S16100A1 Write Cycle / Auto-Precharge CLK t CHI t CKS t CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don’ ...

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... IS42S16100A1 Write Cycle / Full Page CLK t CHI CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = full page Note 1: A8,A9 = Don’ ...

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... IS42S16100A1 Write Cycle / Ping-Pong Operation CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RRD (BANK RCD (BANK 0) ...

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... IS42S16100A1 Read Cycle / Page Mode CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Read Cycle / Page Mode; Data Masking CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Write Cycle / Page Mode CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Write Cycle / Page Mode; Data Masking CLK t CHI t CKS t CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Read Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Write Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Read Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT 0 ...

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... IS42S16100A1 Write Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Read Cycle / Byte Operation CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM DQ8-15 DQ0-7 t RCD t RAS t RC < ...

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... IS42S16100A1 Write Cycle / Byte Operation CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM DQ8-15 DQ0-7 t RCD t RAS t RC < ...

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... IS42S16100A1 Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI t t CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD ...

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... IS42S16100A1 Read Cycle CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’ ...

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... IS42S16100A1 Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT ...

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... IS42S16100A1 Read Cycle / Full Page CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD (BANK 0) t RAS (BANK 0) ...

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... IS42S16100A1 Read Cycle / Ping Pong Operation (Bank Switching CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RRD (BANK ...

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... IS42S16100A1 Write Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’ ...

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... IS42S16100A1 Write Cycle / Auto-Precharge CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT ...

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... IS42S16100A1 Write Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD t RAS t RC < > ACT 0 ...

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... IS42S16100A1 Write Cycle / Ping-Pong Operation (Bank Switching CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RRD (BANK ...

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... IS42S16100A1 Read Cycle / Page Mode CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Read Cycle / Page Mode; Data Masking CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM DQ t RCD t RAS ...

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... IS42S16100A1 Write Cycle / Page Mode CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM DQ t RCD t RAS t RC < > ACT ...

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... IS42S16100A1 Write Cycle / Page Mode; Data Masking CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK DQM RCD ...

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... IS42S16100A1 Read Cycle / Clock Suspend CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Write Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM DQ t RCD t RAS t RC < ...

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... IS42S16100A1 Read Cycle / Precharge Termination CLK t CHI t t CKS CKE t CKA RAS CAS ROW A0- ROW A10 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT 0 ...

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... IS42S16100A1 Write Cycle / Precharge Termination CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 0 DQM DQ t RCD t RAS t RC < > ACT 0 ...

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... IS42S16100A1 Read Cycle / Byte Operation CLK t CHI t t CKS CKE t CKA RAS CAS ROW A0- ROW A10 A11 BANK 1 BANK 0 UDQM LDQM DQ8-15 DQ0-7 t RCD t RAS ...

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... IS42S16100A1 Write Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM DQ8-15 DQ0-7 t RCD t RAS ...

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... IS42S16100A1 Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM ...

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... Order Part No. 6 IS42S16100A1-6T 6 IS42S16100A1-6TL 7 IS42S16100A1-7T 7 IS42S16100A1-7TL 10 IS42S16100A1-10T 10 IS42S16100A1-10TL Speed (ns) Order Part No. 7 IS42S16100A1-7TI 7 IS42S16100A1-7TLI 10 IS42S16100A1-10TI 10 IS42S16100A1-10TLI Integrated Silicon Solution, Inc. — www.issi.com — ISSI ® Package 400-mil TSOP II 400-mil TSOP II, Lead-free 400-mil TSOP II 400-mil TSOP II, Lead-free 400-mil TSOP II 400-mil TSOP II, Lead-free ...

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... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...