is42s16100a1 Integrated Silicon Solution, Inc., is42s16100a1 Datasheet - Page 33

• Manufacturer Part Number: is42s16100a1
• Description: 512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram - Integrated Silicon Solution, Inc
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16100A1
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16100A1 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IS42S16100A1 repeats the operation starting at the
256th cycle with data input returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop
command must be executed to terminate this cycle. A
precharge command
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
08/12/03
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the CAS latency, two clock cycles (t
LDQM pins goes HIGH, the corresponding outputs go to the
HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes
LOW, output is resumed at a time t
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
DQ8-DQ15
DQ
DQ0-DQ 7
UDQM
LDQM
READ (CA=A, BANK 0)
CLK
WRITE A0
D
IN
READ (CA=A, BANK 0)
A0
READ A0
QMD
QMD
D
) after one of the U/
DATA MASK (UPPER BYTE)
IN
later. This output
A1
D
IN
t
DATA MASK (LOWER BYTE)
QMD=2
D
D
A
OUT
OUT
1-800-379-4774
A0
A0
D
IN
must be executed within the ACT to PRE command
period (t
After the period (t
stop following the execution of the burst stop command
has elapsed, the write cycle terminates. This period
(t
latency.
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
DQ8-DQ15) and the LDQM pin controlling lower byte output
(pins DQ0 to DQ7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
D
A1
WBD
OUT
HI-Z
) is zero clock cycles, regardless of the CAS
A1
D
RAS
IN
D
A2
OUT
max.) following the burst stop command.
HI-Z
BURST STOP
A2
WBD
BST
INVALID DATA
D
) required for burst data input to
t
WBD=0
OUT
A3
PRECHARGE (BANK 0)
PRE 0
HI-Z
t
RP
ISSI
Don't Care
33
®