is42s16800a1 Integrated Silicon Solution, Inc., is42s16800a1 Datasheet

is42s16800a1

Manufacturer Part Number

is42s16800a1

Description

8meg 128-mbit Synchronous Dram

Manufacturer

Integrated Silicon Solution, Inc.

Datasheet

1.IS42S16800A1.pdf (63 pages)

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IS42S16800A1

8Meg x16

128-MBIT SYNCHRONOUS DRAM

FEATURES

• Clock frequency: 143 MHz

• Fully synchronous; all signals referenced to a

• Internal bank for hiding row access/precharge

• Power supply

• LVTTL interface

• Programmable burst length

• Programmable burst sequence:

• Auto Refresh (CBR)

• Self Refresh with programmable refresh periods

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

• Burst termination by burst stop and precharge

• Lead-free Availability

Integrated Silicon Solution, Inc. — www.issi.com —

05/01/06

Rev. 00B

time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are

advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

positive clock edge

IS42S16800A1

– (1, 2, 4, 8, full page)

Sequential/Interleave

operations capability

command

3.3V 3.3V

DDQ

1-800-379-4774

KEY TIMING PARAMETERS

OVERVIEW

ISSI

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock

input.The 128Mb SDRAM is organized as follows.

Parameter

CK Cycle Time

CAS Latency = 3

CAS Latency = 2

CK Frequency

CAS Latency = 3

Access Time from Clock

CAS Latency = 3

CAS Latency = 2

IS42S16800A1

2M x16x4 Banks

54-pin TSOPII

's 128Mb Synchronous DRAM achieves high-speed

PRELIMINARY INFORMATION

MAY 2006

ISSI

133

7.5

143

5.4

-7

Unit

Mhz

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